SN65HVD70 Datasheet, PDF (19/41 Pages) Texas Instruments – 3.3-V Full-Duplex RS-485 Transceivers

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SN65HVD70, SN65HVD71, SN65HVD73, SN65HVD74, SN65HVD76, SN65HVD77
SLLSEI9E – MAY 2014 – REVISED OCTOBER 2014
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN65HVD7x family consists of full-duplex RS-485 transceivers commonly used for asynchronous data
transmissions. Full-duplex implementation requires two signal pairs (four wires), and allows each node to
transmit data on one pair while simultaneously receiving data on the other pair.
To eliminate line reflections, each cable end is terminated with a termination resistor, R_(T), whose value matches
the characteristic impedance, Z₀, of the cable. This method, known as parallel termination, allows for higher data
rates over longer cable length.
RD
Y
Z ^R(T)
DE
Master
RE
B
D
R
A ^R(T)
A
R_{(T) B}
R
R
RE
Slave
Z
DE
R_{(T) Y}
DD
AB
ZY
R Slave
D
R RE DE D
Figure 30. Typical RS-485 Network With SN65HVD7x Full-Duplex Transceivers
10.2 Typical Application
A full-duplex RS-485 network consists of multiple transceivers connecting in parallel to two bus cables. On one
signal pair, a master driver transmits data to multiple slave receivers. The master driver and slave receivers may
remain fully enabled at all times. On the other signal pair, multiple slave drivers transmit data to the master
receiver. To avoid bus contention, the slave drivers must be intermittently enabled and disabled such that only
one driver is enabled at any time, as in half-duplex communication. The master receiver may remain fully
enabled at all times.
Because the driver may not be disabled, only one driver should be connected to the bus when using the
SN65HVD71, SN65HVD74, or SN65HVD77 device.
Master Enable Control
Slave Enable Control
V_CC
V_CC
R
A
R
RE
B
R
A
R
RE
B
DE
V_CC
D
Z
D
Y
GND
DE
D
Z
D
Y
GND
Figure 31. Full-Duplex Transceiver Configurations
Copyright © 2014, Texas Instruments Incorporated
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