PCM1737_15 Datasheet, PDF (19/32 Pages) Texas Instruments – DIGITAL-TO-ANALOG CONVERTER

REGISTER 20
B15 B14 B13 B12 B11 B10
B9
B8
B7 B6
B5
B4
B3
B2
B1
B0
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 X4DS FLT1 FLT0 CLKD CLKE FMT2 FMT1 FMT0
R/W
Read/Write Mode Select
When R/W = 0, a Write operation is performed.
When R/W = 1, a Read operation is performed.
Default Value: 0
FMT[2:0]
Audio Interface Data Format
These bits are Read/Write.
Default Value: 000_B
The FMT[2:0] bits are used to select the data format for the serial audio interface. The table below shows the
available format options.
FMT[2:0]
000
001
010
011
100
101
110
111
Audio Data Format Selection
24-Bit Standard Format, Right-Justified Data (default)
20-Bit Standard Format, Right -Justified Data
18-Bit Standard Format, Right-Justified Data
16-Bit Standard Format, Right-Justified Data
I2S Format, 16 to 24 Bits
Right-Justified Format, 16 to 24 Bits
Reserved
Reserved
CLKE
CLKD
CLKO Output Enable
This bit is Read/Write.
Default Value: 0
CLKE = 0
CLKE = 1
CLKO Enabled (default)
CLKO Disabled
The CLKE bit is used to enable or disable the system clock output pin, CLKO. When CLKO is enabled, it will
output either a full or half rate clock, based upon the setting of the CLKD bit. When CLKO is disabled, it is
set to a high impedance state.
CLKO Frequency Selection
This bit is Read/Write.
Default Value: 0
CKLD = 0
CKLD = 1
Full Rate, f_CLKO = f_SCLK (default)
Half Rate, f_CLKO = f_SCLK/2
The CLKD bit is used to select the clock frequency for the CLKO pin.
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PCM1737