OPA4684 Datasheet, PDF (19/33 Pages) Burr-Brown (TI) – Quad, Low-Power, Current-Feedback OPERATIONAL AMPLIFIER

possible to adjust the feedback resistor to hold this band-
width up as the gain is increased. The CFB_PLUS architecture
has reduced the contribution of the inverting input impedance
to provide exceptional bandwidth to higher gains without
adjusting the feedback resistor value. The Typical Character-
istics show the small-signal bandwidth over gain with a fixed
feedback resistor.
Putting a closed-loop buffer between the noninverting and
inverting inputs does bring some added considerations. Since
the voltage at the inverting output node is now the output of
a locally closed-loop buffer, parasitic external capacitance on
this node can cause frequency response peaking for the
transfer function from the noninverting input voltage to the
inverting node voltage. While it is always important to keep
the inverting node capacitance low for any current-feedback
op amp, it is critically important for the OPA4684. External
layout capacitance in excess of 2pF will start to peak the
frequency response. This peaking can be easily reduced by
then increasing the feedback resistor value—but it is prefer-
able, from a noise and dynamic range standpoint, to keep
that capacitance low, allowing a close to nominal 800Ω
feedback resistor for flat frequency response. Very high
parasitic capacitance values on the inverting node (> 5pF)
can possibly cause input stage oscillation that cannot be
filtered by a feedback element adjustment.
At very high gains, 2nd-order effects in the inverting output
impedance cause the overall response to peak up. If desired,
it is possible to retain a flat frequency response at higher
gains by adjusting the feedback resistor to higher values as
the gain is increased. Since the exact value of feedback that
will give a flat frequency response depends strongly in
inverting and output node parasitic capacitance values, it is
best to experiment in the specific board with increasing
values until the desired flatness (or pulse response shape) is
obtained. In general, increasing R_F (and then adjusting R_G to
the desired gain) will move towards flattening the response,
while decreasing it will extend the bandwidth at the cost of
some peaking.
OUTPUT CURRENT AND VOLTAGE
The OPA4684 provides output voltage and current capabili-
ties that can support the needs of driving doubly-terminated
50Ω lines. For a 100Ω load at the gain of +2, (see Figure 1),
the total load is the parallel combination of the 100Ω load and
the 1.6kΩ total feedback network impedance. This 94Ω load
will require no more than 40mA output current to support
the ±3.8V minimum output voltage swing specified for
100Ω loads. This is well under the specified minimum
+110mA/–90mA output current specifications over the full
temperature range.
The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage • current, or V-I product,
which is more relevant to circuit operation. Refer to the
Output Voltage and Current Limitations curve in the Typical
Characteristics. The X- and Y-axes of this graph show the
zero-voltage output current limit and the zero-current output
voltage limit, respectively. The four quadrants give a more
detailed view of the OPA4684’s output drive capabilities.
Superimposing resistor load lines onto the plot shows the
available output voltage and current for specific loads.
The minimum specified output voltage and current over
temperature are set by worst-case simulations at the cold
temperature extreme. Only at cold startup will the output
current and voltage decrease to the numbers shown in the
Electrical Characteristic tables. As the output transistors
deliver power, their junction temperatures will increase, de-
creasing their V_BEs (increasing the available output voltage
swing) and increasing their current gains (increasing the
available output current). In steady-state operation, the avail-
able output voltage and current will always be greater than
that shown in the over temperature specifications since the
output stage junction temperatures will be higher than the
minimum specified operating ambient.
To maintain maximum output stage linearity, no output short-
circuit protection is provided. This will not normally be a
problem since most applications include a series-matching
resistor at the output that will limit the internal power dissipa-
tion if the output side of this resistor is shorted to ground.
However, shorting the output pin directly to a power-supply
pin will, in most cases, destroy the amplifier. If additional
short-circuit protection is required, consider a small-series
resistor in the power-supply leads. This will, under heavy
output loads, reduce the available output voltage swing. A 5Ω
series resistor in each power-supply lead will limit the internal
power dissipation to less than 1W for an output short-circuit
while decreasing the available output voltage swing only
0.25V for up to 50mA desired load currents. This slight drop
in available swing is more if multiple channels are driving
heavy loads simultaneously. Always place the 0.1µF power-
supply decoupling capacitors after these supply current lim-
iting resistors, directly on the supply pins.
DRIVING CAPACITIVE LOADS
One of the most demanding, and yet very common, load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC—including additional
external capacitance which may be recommended to im-
prove ADC linearity. A high-speed, high open-loop gain
amplifier like the OPA4684 can be very susceptible to de-
creased stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin. When the
amplifier’s open-loop output resistance is considered, this
capacitive load introduces an additional pole in the signal
path that can decrease the phase margin. Several external
solutions to this problem have been suggested. When the
primary considerations are frequency response flatness, pulse
response fidelity, and/or distortion, the simplest and most
effective solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor between
the amplifier output and the capacitive load. This does not
eliminate the pole from the loop response, but rather shifts it
and adds a zero at a higher frequency. The additional zero
acts to cancel the phase lag from the capacitive load pole,
thus increasing the phase margin and improving stability.
OPA4684
19
SBOS240G
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