LP2982 Datasheet, PDF (19/28 Pages) National Semiconductor (TI) – Micropower 50 mA Ultra Low-Dropout Regulator

www.ti.com
LP2982
SNVS128K – MARCH 2000 – REVISED JUNE 2016
T_J(MAX) = T_A(MAX) + (R_θJA × P_D(MAX))
(2)
P_D = (T_J(MAX) – T_A(MAX)) / R_θJA
(3)
Unfortunately, this R_θJA is highly dependent on the heat-spreading capability of the particular PCB design, and
therefore varies according to the total copper area, copper weight, and location of the planes. The R_θJA recorded
in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and copper-
spreading area and is to be used only as a relative measure of package thermal performance. For a well-
designed thermal layout, R_θJA is actually the sum of the package junction-to-board thermal resistance (R_θJB) plus
the thermal resistance contribution by the PCB copper area acting as a heat sink.
8.2.2.6 Estimating Junction Temperature
The EIA/JEDEC standard recommends the use of psi (Ψ) thermal characteristics to estimate the junction
temperatures of surface mount devices on a typical PCB board application. These characteristics are not true
thermal resistance values, but rather package specific thermal characteristics that offer practical and relative
means of estimating junction temperatures. These psi metrics are determined to be significantly independent of
copper-spreading area. The key thermal characteristics (Ψ_JT and Ψ_JB) are given in Thermal Information and are
used in accordance with Equation 4 or Equation 5.
T_J(MAX) = T_TOP + (Ψ_JT × P_D(MAX))
where
• P_D(MAX) is explained in Equation 3
• T_TOP is the temperature measured at the center-top of the device package.
(4)
T_J(MAX) = T_BOARD + (Ψ_JB × P_D(MAX))
where
• P_D(MAX) is explained in Equation 3.
• T_BOARD is the PCB surface temperature measured 1 mm from the device package and centered on the
package edge.
(5)
For more information about the thermal characteristics Ψ_JT and Ψ_JB, see Semiconductor and IC Package Thermal
Metrics (SPRA953); for more information about measuring T_TOP and T_BOARD, see Using New Thermal Metrics
(SBVA025); and for more information about the EIA/JEDEC JESD51 PCB used for validating R_θJA, see the TI
Application Report Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs
(SZZA017). These application notes are available at www.ti.com.
8.2.3 Application Curves
Figure 40. 5-V, 2.2-μF ESR Curves
Figure 41. 3-V, 4.7-μF ESR Curves
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: LP2982
Submit Documentation Feedback
19