LM43602-Q1 Datasheet, PDF (19/48 Pages) Texas Instruments – SIMPLE SWITCHER 3.5 V to 36 V 2-A Synchronous Step-Down Voltage Converter

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Feature Description (continued)
LM43602-Q1
SNVSA83A – APRIL 2015 – REVISED MAY 2015
VOUT
R_FBT
C_FF
FB
R_FBB
Figure 34. Feed-Forward Capacitor for Loop Compensation
The feed-forward capacitor C_FF in parallel with R_FBT places an additional zero before the cross over frequency of
the control loop to boost phase margin. The zero frequency can be found by
f_Z-CFF = 1 / ( 2π × R_FBT × C_FF ).
(8)
An additional pole is also introduced with C_FF at the frequency of
f_P-CFF = 1 / (2π × C_FF × (R_FBT // R_FBB )).
(9)
The C_FF should be selected such that the bandwidth of the control loop without the C_FF is centered between f_Z-CFF
and f_P-CFF. The zero f_Z-CFF adds phase boost at the crossover frequency and improves transient response. The
pole f_P-CFF helps maintaining proper gain margin at frequency beyond the crossover.
Designs with different combinations of output capacitors need different C_FF. Different types of capacitors have
different Equivalent Series Resistance (ESR). Ceramic capacitors have the smallest ESR and need the most
C_FF. Electrolytic capacitors have much larger ESR and the ESR zero frequency
f_Z-ESR = 1 / ( 2π × ESR × C_OUT)
(10)
would be low enough to boost the phase up around the crossover frequency. Designs using mostly electrolytic
capacitors at the output may not need any C_FF.
The C_FF creates a time constant with R_FBT that couples in the attenuated output voltage ripple to the FB node. If
the C_FF value is too large, it can couple too much ripple to the FB and affect V_OUT regulation. It could also couple
too much transient voltage deviation and falsely trip PGOOD thresholds. Therefore, C_FF should be calculated
based on output capacitors used in the system. At cold temperatures, the value of C_FF might change based on
the tolerance of the chosen component. This may reduce its impedance and ease noise coupling on the FB
node. To avoid this, more capacitance can be added to the output or the value of C_FF can be reduced. Please
refer to the Detailed Design Procedure for the calculation of C_FF.
8.3.10 Bootstrap Voltage (BOOT)
The driver of the HS switch requires a bias voltage higher than V_IN when the HS switch is ON. The capacitor
connected between CBOOT and SW pins works as a charge pump to boost voltage on the CBOOT pin to (V_SW +
V_CC). The boot diode is integrated on the LM43602-Q1 die to minimize Bill Of Material (BOM). A synchronous
switch is also integrated in parallel with the boot diode to reduce voltage drop on CBOOT. A high quality ceramic
0.47 µF 6.3 V or higher capacitor is recommended for C_BOOT.
8.3.11 Power Good (PGOOD)
The LM43602-Q1 has a built in power-good flag shown on PGOOD pin to indicate whether the output voltage is
within its regulation level. The PGOOD signal can be used for start-up sequencing of multiple rails or fault
protection. The PGOOD pin is an open-drain output that requires a pull-up resistor to an appropriate DC voltage.
Voltage seen by the PGOOD pin should never exceed 12 V. A Resistor divider pair can be used to divide voltage
down from a higher potential. A typical range of pull-up resistor value is 10 kΩ to 100 kΩ.
When the FB voltage is within the power-good band, +4% above and –7% below the internal reference V_REF
typically, the PGOOD switch will be turned off and the PGOOD voltage will be pulled up to the voltage level
defined by the pull-up resistor or divider. When the FB voltage is outside of the tolerance band, +10% above or -
13% below V_REF typically, the PGOOD switch will be turned on and the PGOOD pin voltage will be pulled low to
indicate power bad. Both rising and falling edges of the power-good flag have a built-in 220 µs (typical) deglitch
delay.
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