CDCLVP2108_16 Datasheet, PDF (19/31 Pages) Texas Instruments – 16-LVPECL Output, High-Performance Clock Buffer

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9 Application and Implementation
CDCLVP2108
SCAS878C – MAY 2009 – REVISED JANUARY 2016
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The CDCLVP2108 is a low additive jitter LVPECL fan-out buffer that can generate two copies each of two
independent LVPECL, LVDS, or LVCMOS inputs. The CDCLVP2108 can accept reference clock frequencies up
to 2 GHz while providing low output skew.
9.2 Typical Application
Figure 20 shows a fan-out buffer for line-card application.
2.5 V
2.5 V
156.25 MHz LVPECL
from backplane
96
PRIREF_P
PRIREF_N
105
86 86
CDCLVP21xx
156.25 MHz LVCMOS
Oscillator
2.5 V
SECREF_P
PHY
100
2.5 V _ASIC
250
62.5
FPGA
100
1k
SECREF_N
1k
86 86
CPU
100
86 86
Figure 20. CDCLVP2108 Typical Application
9.2.1 Design Requirements
The CDCLVP2108 shown in Figure 20 is configured to be able to select two inputs: a 156.25-MHz LVPECL clock
from the backplane, or a secondary 156.25-MHz LVCMOS 2.5-V oscillator. Either signal can be then fanned out
to desired devices, as shown.
The configuration example is driving 4 LVPECL receivers in a line-card application with the following properties:
• The PHY device has internal AC coupling and appropriate termination and biasing. The CDCLVP2108 must
be provided with 86-Ω emitter resistors near the driver for proper operation.
• The ASIC is capable of DC coupling with a 2.5-V LVPECL driver such as the CDCLVP2108. This ASIC
features internal termination so no additional components are needed.
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