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ADS8506 Datasheet, PDF (19/35 Pages) Burr-Brown (TI) – 12-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
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ADS8506
SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007
R/C
td1
BUSY
td3
STATUS
External
DATACLK
tw1
tw2
tsu1
td2
td11
Nth Conversion
Error
Correction
tconv
(N+1) th Accquisition
tsu3
tacq
tc2
tw3
tw4
012345
td1
td3
8 9 10 11 12
tsu1
SDATA
TAG
td8
D11 D10 D9 D8 D7 D6
tsu4
th1
T00 T01 T02 T03 T04 T05 T06
Nth Conversion Data
td8
D03 D02 D01 D00 Null T00 Txx
T8 T9 T10 T11 Null T13 Tyy
EXT/INT tied high, CS tied low
tw1 + tsu1 starts READ
Figure 38. Read After Conversion (Discontinuous External DATACLK)
tw1
R/C
td1
BUSY
td3
STATUS
External
DATACLK
tw2
tsu3
tsu1
Nth Conversion
tc2
tw3
tw4
0
1
2
3
4
td10
tconv
5
7
8
9
10 11
SDATA
td8
D11 D10 D9 D8 D7 D6
(N − 1)th Conversion Data
td8
D03 D02 D01 D00
EXT/INT tied high, CS and TAG tied low
Rising DATACLK change DATA, tw1 + tsu1 Starts READ
TAG is not recommended for this mode. There is not enough
time to do so without violating td11.
Figure 39. Read During Conversion (Discontinuous External DATACLK)
td2
Error
Correction
td11
TAG FEATURE
The TAG feature allows the data from multiple ADS8506 converters to be read on a single serial line. The
converters are cascaded together using the DATA pins as outputs and the TAG pins as inputs as illustrated in
Figure 40. The DATA pin of the last converter drives the processor's serial data input. Data is then shifted
through each converter, synchronous to the externally supplied data clock, onto the serial data line. The internal
clock cannot be used for this configuration.
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS8506
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