ADS7871 Datasheet, PDF (19/44 Pages) Texas Instruments – 14-BIT, 48-KSPS, DATA ACQUISITION SYSTEM WITH ANALOG-TO-DIGITAL CONVERTER, MUX, PGA, AND REFERENCE

ADS7871
www.ti.com
SLAS370C − APRIL 2002 − REVISED OCTOBER 2004
Write Operation
To perform a write operation an instruction byte must first be written to the ADS7871 as described previously
(see Figure 17). This instruction determines the target register as well as the word length (8 bits or 16 bits). The
CS pin must be asserted (0) prior to the first active SCLK edge (rising or falling depending on the state of the
RISE/FALL pin) that latches the first bit of the instruction byte. The first active edge after CS must have the first
bit of the instruction byte. The remaining seven bits of the instruction byte are latched on the next seven active
edges of SCLK. CS must remain low for the entire sequence. Setting CS high resets the serial interface.
When starting a conversion by setting the CNV/BSY bit in the Gain/Mux register and/or the Digital I/O register,
the conversion starts on the second falling edge of DCLK after the last active SCLK edge of the write operation.
Figure 19 shows an example of an eight-bit write operation with LSB first and SCLK active on the rising edge.
The double arrows indicate the SCLK transition when data is latched into its destination register.
Instruction Latched
Register is updated
SCLK
DIN
DOUT
ÓÓÓÓÓÓÓÓ^A0 ÓÓÓ^AÓÓÓ¹ ÓÓÓ^A2 ÓÓÓ^A3ÓÓÓ^AÓÓÓ⁴ ÓÓÓ⁰ ÓÓÓ⁰ÓÓÓÓÓÓ⁰ ÓÓÓ^D0ÓÓÓ^DÓÓÓ¹ ÓÓÓ^D2ÓÓÓ^DÓÓÓ³ ÓÓÓ^D4 ÓÓÓ^D5ÓÓÓÓÓÓ^D6 ÓÓÓ^{D7ÓÓÓÓÓ}
CS
Figure 19. Timing Diagram for an 8-Bit Write Operation
Figure 20 shows an example of the timing for a 16-bit write to an even address with LSB first and SCLK active
on the rising edge. Notice that both bytes are updated to their respective registers simultaneously. Also shown
is that the address (ADDR) for the write of the second byte is incremented by one since the ADDR in the
instruction byte was even. For an odd ADDR, the address for the second byte would be ADDR−1.
Instruction Latched
Both Bytes Updated
SCLK
ÓÓ ÓÓ _DIN
ÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓ _DOUT
0 A1 A2 A3 A4 1 0 0 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Data for ADDR
Data for ADDR + 1
CS
Figure 20. Timing Diagram of a 16-Bit Write Operation to an Even Address
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