ADS7029-Q1 Datasheet, PDF (19/32 Pages) Texas Instruments – Small-Size, Low-Power, 8-Bit, 2-MSPS, SAR ADC

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ADS7029-Q1
SBAS811 – JANUARY 2017
8.4.1.2 Offset Calibration During Normal Operation
Offset calibration can be done during normal device operation if at least 32 SCLK falling edges are provided in
one serial transfer frame. During the first 10 SCLKs, the device converts the sample acquired on the CS falling
edge and provides data on the SDO output. The device initiates the offset calibration on the 17th SCLK falling
edge and calibration completes on the 32nd SCLK falling edge. The SDO output remains low after the 10th
SCLK falling edge and SDO goes to tri-state after CS goes high. If the device is provided with less than 32
SCLKs during a serial transfer frame, the OCR is not updated. Table 3 provides the timing parameters for offset
calibration during normal operation.
For subsequent samples, the device adjusts the conversion results with the value stored in the OCR. The
conversion result adjusted with the value stored in the OCR is provided by the device on the SDO output.
Figure 36 shows the timing diagram for offset calibration during normal operation.
f_CLK-CAL
t_CAL
t_ACQ
t_{PH_CS}
t_{SU_CSCK}
t_{D_CKCS}
Table 3. Offset Calibration During Normal Operation
SCLK frequency for calibration
Calibration time during normal operation
Acquisition time
CS high time
Setup time: CS falling to SCLK falling
Delay time: last SCLK falling to CS rising
MIN
15 × t_SCLK
120
t_ACQ
12
10
TYP
Sample
N
t_CONV
CS
t_{SU_CSCK}
t_CAL
MAX
12
UNIT
MHz
ns
ns
ns
ns
ns
t_{PH_CS}
t_ACQ
Sample
N+1
t_{D_CKCS}
SCLK(f_CLK-CAL)
1
2
3
4
9 10
16 17 18
31 32
SDO
0
0 D7 D6
D1 D0
Data for Sample N
Figure 36. Offset Calibration During Normal Operation Timing Diagram
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