ADC14V155_14 Datasheet, PDF (19/29 Pages) Texas Instruments – 155 MSPS, 1.1 GHz Bandwidth A/D Converter with LVDS Outputs

ADC14V155
www.ti.com
SNAS397H – MARCH 2007 – REVISED APRIL 2009
A single-ended to differential conversion circuit is shown in Figure 22. A transformer is preferred for high
frequency input signals. Terminating the transformer on the secondary side provides two advantages. First, it
presents a real broadband impedance to the ADC inputs and second, it provides a common path for the charging
glitches from each side of the differential sample-and-hold circuit.
One short-coming of using a transformer to achieve the single-ended to differential conversion is that most RF
transformers have poor low frequency performance. A differential amplifier can be used to drive the analog inputs
for low frequency applications. The amplifier must be fast enough to settle from the charging glitches on the
analog input resulting from the sample-and-hold operation before the clock goes high and the sample is passed
to the ADC core.
The SFDR performance of the converter depends on the external signal conditioning circuity used, as this affects
how quickly the sample-and-hold charging glitch will settle. An external resistor and capacitor network as shown
in Figure 22 should be used to isolate the charging glitches at the ADC input from the external driving circuit and
to filter the wideband noise at the converter input. These components should be placed close to the ADC inputs
because the analog input of the ADC is the most sensitive part of the system, and this is the last opportunity to
filter that input. For Nyquist applications the RC pole should be at the ADC sample rate. The ADC input
capacitance in the sample mode should be considered when setting the RC pole. For wideband undersampling
applications, the RC pole should be set at about 1.5 to 2 times the maximum input frequency to maintain a linear
delay response.
Input Common Mode Voltage
The input common mode voltage, V_CM, should be in the range of 1.4V to 1.6V and be a value such that the peak
excursions of the analog signal do not go more negative than ground or more positive than 2.6V. It is
recommended to use V_RM (pin 45) as the input common mode voltage.
Reference Pins
The ADC14V155 is designed to operate with an internal 1.0V reference, or an external 1.0V reference, but
performs well with external reference voltages in the range of 0.9V to 1.1V. The internal 1.0 Volt reference is the
default condition when no external reference input is applied to the V_REF pin. If a voltage in the range of 0.9V to
1.1V is applied to the V_REF pin, then that voltage is used for the reference. The V_REF pin should always be
bypassed to ground with a 0.1 µF capacitor close to the reference input pin. Lower reference voltages will
decrease the signal-to-noise ratio (SNR) of the ADC14V155. Increasing the reference voltage (and the input
signal swing) beyond 1.1V may degrade THD for a full-scale input, especially at higher input frequencies.
It is important that all grounds associated with the reference voltage and the analog input signal make connection
to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path.
The Reference Bypass Pins (V_RP, V_RM, and V_RN) are made available for bypass purposes. All these pins should
each be bypassed to ground with a 0.1 µF capacitor. A 0.1 µF and a 10 µF capacitor should be placed between
the V_RP and V_RN pins, as shown in Figure 22. This configuration is necessary to avoid reference oscillation,
which could result in reduced SFDR and/or SNR. V_RM may be loaded to 1mA for use as a temperature stable
1.5V reference. The remaining pins should not be loaded.
Smaller capacitor values than those specified will allow faster recovery from the power down and sleep modes,
but may result in degraded noise performance. Loading any of these pins, other than V_RM, may result in
performance degradation.
The nominal voltages for the reference bypass pins are as follows:
V_RM = 1.5 V
V_RP = V_RM + V_REF / 2
V_RN = V_RM − V_REF / 2
Control Inputs
Power-Down & Sleep (PD/Sleep)
The power-down and sleep modes can be enabled through this three-state input pin. Table 2 shows how to
utilize these options.
Copyright © 2007–2009, Texas Instruments Incorporated
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