ADC128S022_15 Datasheet, PDF (19/29 Pages) Texas Instruments – 8-Channel, 50 kSPS to 200 kSPS, 12-Bit A/D Converter

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ADC128S022
SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015
Typical Application (continued)
Sampling is in fact a modulation process which may result in aliasing of the input signal, if the input signal is not
adequately band limited. The maximum sampling rate of the ADC128S022 when all channels are enabled is, Fs
is calculated by Equation 2:
FSCLK
Fs =
16 ´ 8
(2)
Note that faster sampling rates can be achieved when fewer channels are sampled. Single channel can be
sampled at the maximum rate of Equation 3:
Fs _ sin gle
=
FSCLK
16
(3)
In order to avoid the aliasing, the Nyquist criterion has to be met by Equation 4:
BWsignal £ ^Fs
2
(4)
Therefore it is necessary to place anti-aliasing filters at all inputs of the ADC. These filters may be single-pole
lowpass filters whose pole location has to satisfy, assuming all channels sampled in sequence of Equation 5 and
Equation 6:
1
FSCLK
£
p ´ R ´ C 16 ´ 8
(5)
128
R´C ³
p ´ FSCLK
(6)
With Fsclk = 16 MHz, a good choice for the single-pole filter is:
• R = 100
• C = 33 nF
This reduces the input BW_signal = 48 kHz. The capacitor at the INx input of the device provides not only the
filtering of the input signal, but it also absorbs the charge kick-back from the ADC. The kick-back is the result of
the internal switches opening at the end of the acquisition period.
The VA and VD sources are already separated in this example, due to the design requirements. This also
benefits the overall performance of the ADC, as the potentially noisy VD supply does not contaminate the VA. In
the same vain, further consideration could be given to the SPI interface, especially when the master MCU is
capable of producing fast rising edges on the digital bus signals. Inserting small resistances in the digital signal
path may help in reducing the ground bounce, and thus improve the overall noise performance of the system.
Take care when the signal source is capable of producing voltages beyond VA. In such instances the internal
ESD diodes may start conducting. The ESD diodes are not intended as input signal clamps. To provide the
desired clamping action use Schottky diodes as shown in Figure 38.
8.2.3 Application Curve
Figure 39. Typical Performance
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