ADC121S625 Datasheet, PDF (19/31 Pages) National Semiconductor (TI) – 12-Bit, 50 ksps to 200 ksps, Differential Input, Micro Power Sampling A/D Converter

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ADC121S625
SNAS294B – MAY 2005 – REVISED MARCH 2013
6
+5.3
5
4
Single-Ended
Input
V_A = 5.0V
3
2.8
2.2
2
1
0
-0.3
-1
0.0 0.5
1.0
1.5
2.0
2.5
V_REF (V)
Figure 52. V_CM range for single-ended operation
Differential
Input Signal
Single-Ended
Table 1. Allowable V_CM Range
Minimum V_CM
V_REF / 2 − 0.3V
V_REF − 0.3V
Maximum V_CM
V_A + 0.3V
− ( V_REF / 2 )
V_A + 0.3V
− V_REF
SERIAL DIGITAL INTERFACE
The ADC121S625 communicates via a synchronous 3-wire serial interface as shown in the timing diagram. Each
output bit is sent on the falling edge of SCLK. While most receiving systems will capture the digital output bits on
the rising edge of SCLK, the falling edge of SCLK may be used to capture each bit if the minimum hold time for
D_OUT is acceptable.
Digital Inputs
The Digital inputs consist of the SCLK and CS. A falling CS initiates the conversion and data transfer. The time
between the fall of CS and the second falling edge of SCLK is used to sample the input signal. The data output
is enabled at the second falling edge of SCLK that follows the fall of CS. Since the first bit clocked out is a null
bit, the MSB is clocked out on the third falling edge of SCLK after the fall of CS. For the next 12 SCLK periods
D_OUT will output the conversion result, most significant bit first. After the least significant bit (B0) has been output,
the output data is repeated if CS remains low after the LSB is output, but in a least significant bit first format, with
the LSB being output only once, as indicated in the Figure 3. D_OUT will go into its high impedance state after the
B9 - B10 - B11 sequence. If CS is raised between prior to or at the 15th clock fall, D_OUT will go into its high
impedance state after the LSB (B0) is output and the data is not repeated. Additional clock cycles will not effect
the converter. A new conversion is initiated only when CS has been taken HIGH and returned LOW.
SCLK Input
The SCLK (serial clock) is used to time the conversion process and to clock out the conversion results. This input
is TTL/CMOS compatible. Internal settling time limits the maximum clock frequency and internal capacitor
leakage, or droop, limits the minimum clock frequency. The ADC121S625 offers ensured performance with clock
rates in the range indicated in the ADC121S625 Converter Electrical Characteristics section.
Data Output
The output data format of the ADC121S625 is Two’s Complement, as shown in Table 2. This table indicates the
ideal output code for the given input voltage and does not include the effects of offset, gain error, linearity errors,
or noise.
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