LM3S1636 Datasheet, PDF (187/656 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S1636 Microcontroller
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058
On a read, this register gives the current masked status value of the corresponding interrupt. All of
the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS register
(see page 185).
Masked Interrupt Status and Clear (MISC)
Base 0x400F.E000
Offset 0x058
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PLLLMIS
reserved
BORMIS reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO R/W1C RO
RO
RO
RO R/W1C RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:7
6
5:2
1
0
Name
reserved
PLLLMIS
reserved
BORMIS
reserved
Type
RO
R/W1C
RO
R/W1C
RO
Reset
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PLL Lock Masked Interrupt Status
This bit is set when the PLL T_READY timer asserts. The interrupt is cleared
by writing a 1 to this bit.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
BOR Masked Interrupt Status
The BORMIS is simply the BORRIS ANDed with the mask value, BORIM.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
July 24, 2012
187
Texas Instruments-Production Data