TSC2046_16 Datasheet, PDF (18/32 Pages) Texas Instruments – Low-Voltage I/O TOUCH SCREEN CONTROLLER

TSC2046
SBAS265G − OCTOBER 2002 − REVISED JANUARY 2008
SYMBOL
tACQ
tDS
tDH
tDO
tDV
tTR
tCSS
tCSH
tCH
tCL
tBD
tBDV
tBTR
DESCRIPTION
Acquisition Time
DIN Valid Prior to DCLK Rising
DIN Hold After DCLK High
DCLK Falling to DOUT Valid
CS Falling to DOUT Enabled
CS Rising to DOUT Disabled
CS Falling to First DCLK Rising
CS Rising to DCLK Ignored
DCLK High
DCLK Low
DCLK Falling to BUSY Rising/Falling
CS Falling to BUSY Enabled
CS Rising to BUSY Disabled
+VCC S 2.7V, +VCC S IOVDD S 1.5V, CLOAD = 50pF
MIN
TYP
MAX
1.5
100
50
200
200
200
100
10
200
200
200
200
200
Table 6. Timing Specifications, T_A = −405C to +855C
www.ti.com
UNITS
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS
DCLK
DIN
BUSY
DOUT
1
S
A2
A1
A0
SER/
M O D E _{DFR PD1 PD0}
15 1
S
A2
A1
A0
SER/
M O D E _DFR PD1 PD0
Power−Down
15 1
S A2 A1 A0
11 10 9 8 7 6 5 4 3 2 1 0
11 10 9 8 7
Figure 13. Maximum Conversion Rate, 15 Clocks-per-Conversion
Data Format
The TSC2046 output data is in Straight Binary format, as
shown in Figure 14. This figure shows the ideal output
code for the given input voltage and does not include the
effects of offset, gain, or noise.
8-Bit Conversion
The TSC2046 provides an 8-bit conversion mode that can
be used when faster throughput is needed and the digital
result is not as critical. By switching to the 8-bit mode, a
conversion is complete four clock cycles earlier. Not only
does this shorten each conversion by four bits (25% faster
throughput), but each conversion can actually occur at a
faster clock rate. This is because the internal settling time
of the TSC2046 is not as critical—settling to better than 8
bits is all that is needed. The clock rate can be as much as
50% faster. The faster clock rate and fewer clock cycles
combine to provide a 2x increase in conversion rate.
11...111
11...110
11...101
FS = Full− Scale Voltage = V_REF(1)
1LSB = V_REF(1)/4096
1LSB
00...010
00...001
00...000
0V
FS − 1LSB
Input Voltage⁽²⁾ (V)
NOTES: (1) Reference voltage at converter: +REF − (−REF); see Figure 2.
(2) Input voltage at converter, after multiplexer: +IN − (−IN); see
Figure 2.
Figure 14. Ideal Input Voltages and Output Codes
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