TMS370C756 Datasheet, PDF (18/75 Pages) Texas Instruments – 8-BIT MICROCONTROLLER

TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997
interrupts (continued)
TIMER 2A
Overflow
Compare1
Ext Edge
Compare2
Input Capture 1
Input Capture 2
TIMER 1
Overflow
Compare1
Ext Edge
Compare2
Input Capture 1
Watchdog
EXT INT 3
INT 3
INT3 PRI
EXT INT 2
INT 2
EXT INT1
INT1
INT2 PRI
CPU
NMI
T2A PRI
T1 PRI
AD INT
AD PRI
SCI INT
TX
RX
SPI INT
SPI PRI
INT1 PRI
STATUS REG
IE1
IE2
Enable
Priority
Logic
Level 1 INT
Level 2 INT
A/D
TXPRI
RXPRI
BRKDT
TXRDY
RXRDY
SPI
Figure 4. Interrupt Control
On-chip peripheral functions generate six of the system interrupts. Three external interrupts also are supported.
Software configuration of the external interrupts is performed through the INT1, INT2, and INT3 control registers
in PF frame 1. Each external interrupt is individually software configurable for input polarity (rising or falling
edge) for ease of system interface. External interrupt INT1 is software configurable as either a maskable or
non-maskable interrupt. When INT1 is configured as nonmaskable, it cannot be masked by the individual- or
global-enable mask bits. The INT1 NMI bit is protected during non-privileged operation and, therefore, should
be configured during the initialization sequence following reset. To maximize pin flexibility, external interrupts
INT2 and INT3 can be software configured as general purpose input/output pins if the interrupt function is not
required (INT1 can be similarly configured as an input pin). Table 12 shows the interrupt vector sources,
corresponding addresses, and hardware priorities.
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