TLV62065-Q1 Datasheet, PDF (18/27 Pages) Texas Instruments – 3-MHz 2-A Step-Down Converter in 2-mm x 2-mm SON Package

TLV62065-Q1
SLVSB92A – JANUARY 2012 – REVISED MARCH 2012
www.ti.com
Output Capacitor Selection
The advanced fast-response voltage-mode control scheme of the TLV62065-Q1 allows the use of tiny ceramic
capacitors. Ceramic capacitors with low ESR values have the lowest output-voltage ripple and are
recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V- and Z5U-dielectric
capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies
and may not be used. For most applications, a nominal 10-µF or 22-µF capacitor is suitable. In small ceramic
capacitors, the dc-bias effect decreases the effective capacitance. Therefore a 22-µF capacitor can be used for
output voltages higher than 2 V; see the list of capacitors, Table 3.
In case additional ceramic capacitors in the supplied system are connected to the output of the dc-dc converter,
the output capacitor C_OUT must be decreased in order not to exceed the recommended effective capacitance
range. In this case, a loop stability analysis must be performed as described later.
At nominal load current, the device operates in PWM mode and the RMS ripple current is calculated as:
I_RMSCout + Vout
1
*
Vout
Vin
Lƒ
1
2 ^Ǹ3
(3)
Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low-ESR input capacitor is
required for best input voltage filtering and minimizing interference with other circuits caused by high input
voltage spikes. For most applications a 10-µF ceramic capacitor is recommended. The input capacitor can be
increased without any limit for better input voltage filtering.
Take care when using only small ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output or VIN step on
the input can induce ringing at the V_IN pin. This ringing can couple to the output and be mistaken as loop
instability, or could even damage the part by exceeding the maximum ratings.
CAPACITANCE
10 μF
22 μF
22 µF
10 µF
Table 3. List of Capacitors
TYPE
GRM188R60J106M
GRM188R60G226M
CL10A226MQ8NRNC
CL10A106MQ8NRNC
SIZE [mm]
0603: 1.6 × 0.8 × 0.8
0603: 1.6 × 0.8 × 0.8
0603: 1.6 × 0.8 × 0.8
0603: 1.6 × 0.8 × 0.8
SUPPLIER
Murata
Murata
Samsung
Samsung
CHECKING LOOP STABILITY
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signal
• Switching node, SW
• Inductor current, I_L
• Output ripple voltage, V_OUT(AC)
These are the basic signals that must be measured when evaluating a switching converter. When the switching
waveform shows large duty cycle jitter, or the output voltage or inductor current shows oscillations, the regulation
loop may be unstable. This is often a result of board layout and/or wrong L-C output filter combinations. As a
next step in the evaluation of the regulation loop, the transient response of the load is tested. During the time
between the application of the load transient and the turnon of the P-channel MOSFET, the output capacitor
must supply all of the current required by the load. V_OUT immediately shifts by an amount equal to Δ_I(LOAD) ×
ESR, where ESR is the effective series resistance of C_OUT. Δ_I(LOAD) begins to charge or discharge C_O, generating
a feedback error signal used by the regulator to return V_OUT to its steady-state value. The results are most easily
interpreted when the device operates in PWM mode at medium-to-high load currents.
During this recovery time, V_OUT can be monitored for settling time, overshoot, or ringing; that helps evaluate
stability of the converter. Without any ringing, the loop has usually more than 45° of phase margin.
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