THS5661_05 Datasheet, PDF (18/30 Pages) Texas Instruments – 12-BIT, 100 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER

THS5661
12-BIT, 100 MSPS, CommsDAC™
DIGITAL-TO-ANALOG CONVERTER
SLAS200A – MAY 1999 – REVISED JULY 1999
APPLICATION INFORMATION
analog current outputs
Figure 26 shows a simplified schematic of the current source array output with corresponding switches.
Differential PMOS switches direct the current of each individual PMOS current source to either the positive
output node IOUT1 or its complementary negative output node IOUT2. The output impedance is determined
by the stack of the current sources and differential switches, and is typically >300 kΩ in parallel with an output
capacitance of 5 pF.
Output nodes IOUT1 and IOUT2 have a negative compliance voltage of –1 V, determined by the CMOS process.
Beyond this value, transistor breakdown may occur, resulting in reduced reliability of the THS5661 device. The
positive output compliance depends on the full-scale output current IOUT_FS and positive supply voltage AV_DD.
The positive output compliance equals 1.25 V for AV_DD = 5 V and IOUT_FS = 20 mA. Exceeding the positive
compliance voltage adversely affects distortion performance and integral nonlinearity. The optimum distortion
performance for a single-ended or differential output is achieved when the maximum full-scale signal at IOUT1
and IOUT2 does not exceed 0.5 V (e.g. when applying a 50 Ω doubly terminated load for 20 mA full-scale output
current). Applications requiring the THS5661 output (i.e., OUT1 and/or OUT2) to extend its output compliance
should size R_LOAD accordingly.
AVDD
Current
Sources
Switches
IOUT1
RLOAD
IOUT2
RLOAD
Current Source Array
Figure 26. Equivalent Analog Current Output
Figure 27(a) shows the typical differential output configuration with two external matched resistor loads. The
nominal resistor load of 50 Ω will give a differential output swing of 2 V_PP when applying a 20 mA full-scale output
current. The output impedance of the THS5661 depends slightly on the output voltage at nodes IOUT1 and
IOUT2. Consequently, for optimum dc integral nonlinearity, the configuration of Figure 27(b) should be chosen.
In this I–V configuration, terminal IOUT1 is kept at virtual ground by the inverting operational amplifier. The
complementary output should be connected to ground to provide a dc current path for the current sources
switched to IOUT2. Note that the INL/DNL specifications for the THS5661 are measured with IOUT1 maintained
at virtual ground. The amplifier’s maximum output swing and the DAC’s full-scale output current determine the
value of the feedback resistor R_FB. Capacitor C_FB filters the steep edges of the THS5661 current output, thereby
reducing the operational amplifier slew-rate requirements. In this configuration, the op amp should operate on
a dual supply voltage due to its positive and negative output swing. Node IOUT1 should be selected if a
single-ended unipolar output is desirable.
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