THS4051 Datasheet, PDF (18/36 Pages) Texas Instruments – 70-MHz HIGH-SPEED AMPLIFIERS

THS4051
THS4052
SLOS238D − MAY 1999 − REVISED AUGUST 2008
APPLICATION INFORMATION
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OFFSET VOLTAGE
The output offset voltage, (V_OO) is the sum of the input offset voltage (V_IO) and both input bias currents (I_IB) times the
corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:
RF
RG
+IIB−
−
+
VO
RS
−
+
+IIB+
VIO
ǒ Ǔ ǒ Ǔ VOO + VIO
1
)
RF
RG
" IIB₎ RS
1
)
RF
RG
" IIB_* RF
Figure 47. Output Offset Voltage Model
OPTIMIZING UNITY GAIN RESPONSE
Internal frequency compensation of the THS405x was selected to provide very wideband performance yet still maintain
stability when operated in a noninverting unity gain configuration. When amplifiers are compensated in this manner there
is usually peaking in the closed loop response and some ringing in the step response for very fast input edges, depending
upon the application. This is because a minimum phase margin is maintained for the G=+1 configuration. For optimum
settling time and minimum ringing, a feedback resistor of 620 Ω should be used as shown in Figure 48. Additional
capacitance can also be used in parallel with the feedback resistance if even finer optimization is required.
Input
+
THS405x
_
Output
620 Ω
Figure 48. Noninverting, Unity Gain Schematic
18