PCM5252 Datasheet, PDF (18/119 Pages) Texas Instruments – Purepath Smart Amp PCM5252 4.2-VRMS DirectPath, 114-dB Audio Stereo Differential-

PCM5252
SLASE63 – NOVEMBER 2014
www.ti.com
9.4 Audio Data Interface
9.4.1 Audio Serial Interface
The audio interface port is a 3-wire serial port with the signals LRCK, BCK, and DIN. BCK is the serial audio bit
clock, used to clock the serial data present on DIN into the serial shift register of the audio interface. Serial data
is clocked into the PCM5252 on the rising edge of BCK. LRCK is the serial audio left/right word clock. LRCK
polarity for Left/Right is given by the format selected.
CONTROL MODE
Software Control
(SPI or I²S)
Hardware Control
Table 4. PCM5252 Audio Data Formats, Bit Depths and Clock Rates
FORMAT
I²S/LJ
TDM/DSP
I²S/LJ
DATA BITS
32, 24, 20, 16
32, 24, 20, 16
32, 24, 20, 16
MAX LRCK
FREQUENCY [f_S]
Up to 192kHz
384kHz
Up to 48kHz
96kHz
192kHz
Up to 192kHz
384kHz
SCK RATE [x f_S]
128 – 3072
64, 128
128 – 3072
128 – 512
128, 192, 256
128 – 3072
64, 128
BCK RATE [x f_S]
64, 48, 32
64, 48, 32
125, 256
125, 256
128
64, 48, 32
64, 48, 32
The PCM5252 requires the synchronization of LRCK and system clock, but does not need a specific phase
relation between LRCK and system clock.
If the relationship between LRCK and system clock changes more than ±5 SCK, internal operation is initialized
within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between
LRCK and system clock is completed.
If the relationship between LRCK and BCK are invalid more than 4 LRCK periods, internal operation is initialized
within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between
LRCK and BCK is completed.
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