PCM1789-Q1 Datasheet, PDF (18/41 Pages) Texas Instruments – 24-Bit, 192-kHz Sampling, Enhanced Multi-Level ΔΣ, Stereo, Audio Digital-to-Analog Converter

PCM1789-Q1
SBAS546 – MARCH 2011
AUDIO INTERFACE TIMING
Figure 27 and Table 5 describe the detailed audio interface timing specifications.
BCK
(Input)
LRCK
(Input)
DIN
(Input)
t_BCH
t_BCL
t_BCY
t_LRH
t_LRS
t_DIS
t_DIH
t_LRW
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1.4 V
1.4 V
1.4 V
Figure 27. Audio Interface Timing Diagram for Left-Justified, Right-Justified, I²S, and DSP Data Formats
SYMBOL
t_BCY
t_BCH
t_BCL
t_LRW
t_LRS
t_LRH
t_DIS
t_DIH
Table 5. Timing Requirements for Figure 27
DESCRIPTION
BCK cycle time
BCK pulse width high
BCK pulse width low
LRCK pulse width high (LJ, RJ and I²S formats)
LRCK pulse width high (DSP format)
LRCK setup time to BCK rising edge
LRCK hold time to BCK rising edge
DIN setup time to BCK rising edge
DIN hold time to BCK rising edge
MIN
75
35
35
1/(2 × f_S)
t_BCY
10
10
10
10
TYP
MAX
1/(2 × f_S)
t_BCY
UNIT
ns
ns
ns
sec
sec
ns
ns
ns
ns
18
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