LM3S1110 Datasheet, PDF (18/539 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
Register 3:
Register 4:
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Register 7:
Register 8:
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Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 355
Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 356
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 357
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 358
Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 359
Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 360
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 361
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 362
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 363
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 364
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 365
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 366
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 367
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 368
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 369
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 370
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 371
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 372
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 373
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 382
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 384
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 386
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 388
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 389
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 390
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 391
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 393
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 395
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 397
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 399
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 400
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 401
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 403
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 404
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 405
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 406
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 407
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 408
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 409
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 410
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 411
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 412
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 413
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 414
Synchronous Serial Interface (SSI) ............................................................................................ 415
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 428
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 430
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 432
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July 15, 2014
Texas Instruments-Production Data