DAC5574 Datasheet, PDF (18/32 Pages) Texas Instruments – QUAD, 8-BIT, LOW-POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL TO ANALOG CONVERTER

DAC5574
SLAS407 – DECEMBER 2003
www.ti.com
Master Transmitter Writing to a Slave Receiver (DAC5574) in Standard/Fast Modes
All write access sequences begin with the device address (with R/W = 0) followed by the control byte. This
control byte specifies the operation mode of DAC5574 and determines which channel of DAC5574 is being
accessed in the subsequent read/write operation. The LSB of the control byte (PD0-Bit) determines if the
following data is power-down data or regular data.
With (PD0-Bit = 0) the DAC5574 expects to receive data in the following sequence HIGH-BYTE –LOW-BYTE –
HIGH-BYTE – LOW-BYTE..., until a STOP Condition or REPEATED START Condition on the I²C-Bus is
recognized (refer to the DATA INPUT MODE section of Table 4).
With (PD0-Bit = 1) the DAC5574 expects to receive 2 Bytes of power-down data (refer to the POWER DOWN
MODE section of Table 4).
Table 4. Write Sequence in F/S Mode
DATA INPUT MODE
Transmitter
MSB 6
Master
Master
1
0
DAC5574
Master
0
0
DAC5574
Master
D7 D6
DAC5574
Master
x
x
DAC5574
Master
POWER DOWN MODE
Transmitter
MSB 6
Master
Master
1
0
DAC5574
Master
0
0
DAC5574
Master
PD1 PD2
DAC5574
Master
x
x
DAC5574
Master
5
4
3
2
Start
0
1
1
A1
DAC5574 Acknowledges
Load 1 Load 0
x Buff Sel 1
DAC5574 Acknowledges
D5
D4
D3
D2
DAC5574 Acknowledges
x
x
x
x
DAC5574 Acknowledges
Data or Stop or Repeated Start⁽¹⁾
1
A0
Buff Sel 0
D1
x
LSB
R/W
Comment
Begin sequence
Write addressing (R/W=0)
PD0 Control byte (PD0=0)
D0 Writing data word, high byte
x Writing data word, low byte
Data or done⁽²⁾
5
0
Load 1
0
x
4
3
2
Start
1
1
A1
DAC5574 Acknowledges
Load 0
x Buff Sel 1
DAC5574 Acknowledges
0
0
0
DAC5574 Acknowledges
x
x
x
DAC5574 Acknowledges
Stop or Repeated Start⁽¹⁾
1
A0
Buff Sel 0
0
x
LSB Comment
Begin sequence
R/W Write addressing (R/W=0)
PD0 Control byte (PD0 = 1)
0 Writing data word, high byte
x Writing data word, low byte
Done
(1) Use repeated START to secure bus operation and loop back to the stage of write addressing for next Write.
(2) Once DAC5574 is properly addressed and control byte is sent, HIGH–BYTE–LOW–BYTE sequences can repeat until a STOP condition
or repeated START condition is received.
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