BQ77904_17 Datasheet, PDF (18/45 Pages) Texas Instruments – 3-5S Ultra Low-Power Voltage, Current, Temperature, and Open Wire Stackable Lithium-ion Battery Protector

bq77904, bq77905
SLUSCM3E – JUNE 2016 – REVISED MARCH 2017
www.ti.com
Table 5. Fault Condition, State, and Recovery Methods
FAULT
CTRC disabled
CTRD disabled
OV
UV
OW
OCD1, OCD2,
SCD
OTC ⁽¹⁾
OTD ⁽¹⁾
UTC ⁽¹⁾
UTD ⁽¹⁾
FAULT TRIGGER
CONDITION
CTRC disabled for delgitch
delay time
CTRD disabled for delgitch
delay time
V(Cell) rises above V_OV for
delay time
V(Cell) drops below V_UV for
delay time
VC_X – VC_X-1 < V_OW for delay
time
(VSRP - VSRN) < VOCD1,
VOCD2, or VSCD for delay
time
Temperature rises above
T_OTC for delay time
Temperature rises above
T_OTD for delay time
Temperature drops below
T_UTC for delay time
Temp drops below T_UTD for
delay time
CHG DSG
RECOVERY METHOD
OFF
— CTRC must be enabled for delgitch delay time
—
OFF CTRD must be enabled for delgitch delay time
TRIGGER DELAY
RECOVERY
DELAY
t_{CTRDEG_ON}
t_{CTRDEG_OFF}
OFF
—
OFF
OFF
OFF
OFF
OFF
OFF
— V(Cell) drops below V_OV – V_{HYS_OV} for delay
t_{OVn_DELAY}
OFF
OFF
OFF
—
V(Cell) rises above V_UV + V_{HYS_UV} for delay
t_{UVn_DELAY}
Bad VC_X recovers such that VC_X – VC_X-1 > V_OW +
V_{OW_HYS} for delay
Recovery delay expires, OR
LD detects < V_LDT, OR
Recovery delay expires + LD detects < V_LDT
t_{OWn_DELAY}
t_{OCD1_DELAY,}
t_{OCD2_DELAY,}
t_{SCD_DELAY,}
t_{CD_REC}
Temp drops below T_OTC – T_{OTC_REC} for delay
t_{OTC_DELAY}
OFF
—
Temp drops below T_OTD – T_{OTD_REC} for delay
Temperature rises above T_UTC + T_{UTC_REC} for
delay
OFF Temp rises above T_UTD + T_{UTD_REC} for delay
t_{OTD_DELAY}
t_{UTC_DELAY}
t_{UTD_DELAY}
(1) T_UTC, T_UTD, T_{UTC_REC}, and T_{UTD_REC} correspond to the temperature produced by V_UTC, V_UTD, V_{UTC_REC}, and V_{UTD_REC} of the selected
thermistor resistance.
For bq77904 and bq77905 devices to prevent CHG FET damage, there are times when the CHG FET may be
enabled even though an OV, UTC, OTC or CTRC low event has occurred. See the State Comparator section for
details.
8.3.4 Configuration CRC Check And Comparator Built-In-Self-Test
To improve reliability, the device has built in CRC check for all the factory-programmable configuration, such as
the thresholds and delay time setting. When the device is set up in the factory, a corresponding CRC value is
also programmed to the memory. During normal operation, the device compares the configuration setting against
the programmed CRC periodically. A CRC error will reset the digital circuitry and increment the CRC fault
counter. The digital reset forces the device to reload the configuration as an attempt to correct the configurations.
A correct CRC check reduces the CRC fault counter. Three CRC faults counts will turn off both the CHG and
DSG drivers. If FETs are opened due to CRC error, only a POR can recover the FET state and reset the CRC
fault.
In addition to the CRC check, the device also has built-in-self-test (BIST) on the comparators. The BIST runs in a
scheduler, each comparator is checked for a period of time. If a fault is detected for the entire check period, the
particular comparator is considered at fault, and both the CHG and DSG FETs is turned off. The BIST continuous
to run by the scheduler even if a BIST fault is detected. If the next BIST result is good, the FET driver resumes
normal operation.
The CRC check and BIST check do not affect the normal operation of the device. However, there is not specific
indication when a CRC or BIST error is detected besides turning off both CHG and DSG drivers. If there is no
voltage, current or temperature fault condition present, but CHG and DSG drivers remain off, it is possible either
CRC or BIST error is detected. User can POR the device to reset the device.
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