ADS5424-SP Datasheet, PDF (18/22 Pages) Texas Instruments – CLASS V, 14-BIT, 105-MSPS ANALOG-TO-DIGITAL CONVERTER

ADS5424-SP
SLWS194B – MAY 2008 – REVISED MARCH 2012
www.ti.com
Because the ADS5424 recommended input common-mode voltage is 2.4 V, the THS4509 is operated from a
single power supply input with V_S+ = 5 V and V_S– = 0 V (ground). This maintains maximum headroom on the
internal transistors of the THS4509.
CLOCK INPUTS
The ADS5424 clock input can be driven with either a differential clock signal or a single-ended clock input, with
little or no difference in performance between both configurations. In low-input-frequency applications, where
jitter may not be a big concern, the use of single-ended clock (see Figure 21) could save cost and board space
without any trade-off in performance. When driven on this configuration, it is best to connect CLKM (pin 11) to
ground with a 0.01-μF capacitor, while CLKP is ac-coupled with a 0.01-μF capacitor to the clock source, as
shown in Figure 22.
Square Wave or
Sine Wave
0.01 µF
CLK
ADS5424M
CLK
0.01 µF
Figure 21. Single-Ended Clock
Clock
Source
0.1 µF _1:4
CLK
MA3X71600LCT−ND
ADS5424
M
CLK
Figure 22. Differential Clock
For jitter sensitive applications, the use of a differential clock has advantages (as with any other ADCs) at the
system level. The first advantage is that it allows for common-mode noise rejection at the PCB level. A further
analysis (see Clocking High Speed Data Converters, SLYT075) reveals one more advantage. The following
formula describes the different contributions to clock jitter:
(Jittertotal)² = (EXT_jitter)² + (ADC_jitter)² = (EXT_jitter)² + (ADC_int)² + (K/clock_slope)²
The first term represents the external jitter, coming from the clock source, plus noise added by the system on the
clock distribution, up to the ADC. The second term is the ADC contribution, which can be divided in two portions.
The first does not depend directly on any external factor. The second contribution is a term inversely proportional
to the clock slope. The faster the slope, the smaller this term will be. As an example, the ADC jitter contribution
could be computed from a sinusoidal input clock of 3-V_pp amplitude and Fs = 80 MSPS:
ADC_jitter = sqrt ((150 fs)² + (5 × 10^–5/(1.5 × 2 × PI × 80 × 10⁶))²) = 164 fs
The use of differential clock allows for the use of bigger clock amplitudes without exceeding the absolute
maximum ratings. This, on the case of sinusoidal clock, results on higher slew rates, which minimize the impact
of the jitter factor inversely proportional to the clock slope.
Figure 23 shows this approach. The back-to-back Schottky can be added to limit the clock amplitude in cases
where this would exceed the absolute maximum ratings, even when using a differential clock.
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