ADC16V130_15 Datasheet, PDF (18/31 Pages) Texas Instruments – 130 MSPS A/D Converter With LVDS Outputs

ADC16V130
SNAS458E – NOVEMBER 2008 – REVISED MARCH 2013
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Figure 24. S11 Curve of Input Circuit
CLOCK INPUT CONSIDERATIONS
Clock Input Modes
The ADC16V130 provides a low additive jitter differential clock receiver for optimal dynamic performance at wide
input frequency range. Input common mode of the clock receiver is internally biased at V_A1.8/2 through a 10 kΩ
each to be driven by DC coupled clock input as shown in Figure 25. However while DC coupled clock input
drives CLK+ and CLK-, it is recommend the common mode (average voltage of CLK+ and CLK-) not to be higher
than V_A1.8/2 in order to prevent substantial tail current reduction, which might cause lowered jitter performance.
Meanwhile, CLK+ and CLK- should not become lower than AGND. A high speed back-to-back diode connected
between CLK+ and CLK- could limit the maximum swing, but this could cause signal integrity concerns when the
diode turns on and reduce load impedance instantaneously.
A preferred differential clocking through a transformer coupled is shown in Figure 26. A 0.1μF decoupling
capacitor on the center tap of the secondary ports of a flux type transformer stabilizes clock input common mode.
Differential clocking increases the maximum amplitude of the clock input at the pins twice as large as that with
singled-ended mode as shown in Figure 27. Clock amplitude is recommended to be as large as possible while
CLK+ and CLK- both never exceed supply rails of V_A1.8 and AGND. With a given equivalent input noise of the
differential clock receiver shown in Figure 25, larger clock amplitude at CLK+ and CLK- pins increases its slope
around zero-crossing point so that higher signal-to-noise could be obtained by reducing the noise contributed by
clock signal path.
V_A1.8
CLK +
CLK -
10k 10k
V_A1.8
2
Figure 25. Equivalent Clock Receiver
The differential receiver of the ADC16V130 has excellent low noise floor but its bandwidth is wide as multiple
times of clock rate. The wide band noise folds back to nyquist frequency band in frequency domain at ADC
output. Increased slope of the input clock lowers the equivalent noise contributed by the differential receiver.
A band-pass filter (BPF) with narrow pass band and low insertion loss could be added on the clock input signal
path when wide band noise of clock source is noticeably large compared to the input equivalent noise of the
differential clock receiver.
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