ADC10040_15 Datasheet, PDF (18/27 Pages) Texas Instruments – 55.5 mW A/D Converter

ADC10040
SNAS224M – JULY 2003 – REVISED APRIL 2013
2.5V Max
V_CM + 1V
www.ti.com
V_CM
V_CM - 1V
0V Min
Figure 39. Input Voltage Waveform for a 2V_P-P Single Ended Input
A single ended input signal is shown in Figure 39.
The internal switching action at the analog inputs causes energy to be output from the input pins. As the driving
source tries to compensate for this, it adds noise to the signal. To minimize the effects of this, use 18Ω series
resistors at each of the signal inputs with a 25 pF capacitor across the inputs, as shown in Figure 40. These
components should be placed close to the ADC because the input pins of the ADC is the most sensitive part of
the system and this is the last opportunity to filter the input. The two 16Ω resistors and the 24 pF capacitor,
together with the 4 pF ADC input capacitance, form a low-pass filter with a -3 dB frequency of 177 MHz.
CLK PIN
The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock
signal in the frequency range indicated in the AC Electrical Characteristics Table with rise and fall times of less
than 2 ns. The trace carrying the clock signal should be as short as possible and should not cross any other
signal line, analog or digital, not even at 90°. The CLK signal also drives an internal state machine. If the CLK is
interrupted, or its frequency is too low, the charge on internal capacitors can dissipate to the point where the
accuracy of the output data will degrade. This is what limits the lowest sample rate. The duty cycle of the clock
signal can affect the performance of any A/D Converter. Because achieving a precise duty cycle is difficult, the
ADC10040 is designed to maintain performance over a range of duty cycles. While it is specified and
performance is ensured with a 50% clock duty cycle, performance is typically maintained with minimum clock low
and high times indicated in the AC Electrical Characteristics Table. Both minimum high and low times may not be
held simultaneously.
STBY PIN
The STBY pin, when high, holds the ADC10040 in a power-down mode to conserve power when the converter is
not being used. The power consumption in this state is 13.5 mW. The output data pins are undefined in this
mode. Power consumption during power-down is not affected by the clock frequency, or by whether there is a
clock signal present. The data in the pipeline is corrupted while in the power down.
DF PIN
The DF (Data Format) pin, when high, forces the ADC10040 to output the 2’s complement data format. When DF
is tied low, the output format is offset binary.
IRS PIN
The IRS (Input Range Select) pin defines the input signal amplitude that will produce a full scale output. The
table below describes the function of the IRS pin.
IRS Pin
V_DDA
V_SSA
Floating
Table 1. IRS Pin Functions
Full-Scale Input
2.0V_P-P
1.5V_P-P
1.0V_P-P
18
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