TMS320VC549_16 Datasheet, PDF (17/64 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

TMS320VC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS078G − SEPTEMBER 1998 − REVISED OCTOBER 2004
divide-by-two/divide-by-four clock option − PLL disabled (continued)
timing requirements for divide-by-two/divide-by-four clock option − PLL disabled (see Figure 3)
549-80
549-100
MIN MAX MIN MAX
549-120
MIN MAX
UNIT
tc(CI) Cycle time, X2/CLKIN
20‡
† _20‡
† _20‡
† _ns
tf(CI) Fall time, X2/CLKIN
8
8
8 ns
tr(CI) Rise time, X2/CLKIN
8
8
8 ns
tw(CIL) Pulse duration, X2/CLKIN low
5
†
5
†
5
† _ns
tw(CIH) Pulse duration, X2/CLKIN high
5
†
5
†
5
† _ns
† _{This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies}
approaching 0 Hz.
‡ _{It is recommended that the PLL clocking option be used for maximum frequency operation.}
X2/CLKIN
tc(CI)
tw(CIH)
tr(CI)
tf(CI)
tc(CO)
td(CIH-CO)
tw(CIL)
tf(CO)
tr(CO)
tw(COH)
tw(COL)
CLKOUT
Figure 3. External Divide-by-Two Clock Timing
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