TLV320AIC1110_14 Datasheet, PDF (17/41 Pages) Texas Instruments – PCM CODEC

timing requirements
clock (2.048-MHz CLK)
PARAMETER
tt
f(mclk)
Transition time, MCLK
MCLK frequency
MCLK jitter
Number of PCMCLK clock cycles per PCMSYN frame
tc(PCMCLK) PCMCLK clock period
Duty cycle, PCMCLK
transmit (2.048-MHz CLK) (see Figure 1)
PARAMETER
tsu(PCMSYN) Setup time, PCMSYN high before falling edge of PCMCLK
th(PCMSYN) Hold time, PCMSYN high after falling edge of PCMCLK
receive (2.048-MHz CLK) (see Figure 2)
PARAMETER
tsu(PCSYN)
th(PCSYN)
tsu(PCMI)
th(PCMI)
Setup time, PCMSYN high before falling edge of PCMCLK
Hold time, PCMSYN high after falling edge of PCMCLK
Setup time, PCMI high or low before falling edge of PCMCLK
Hold time, PCMI high or low after falling edge of PCMCLK
clock (128-kHz CLK)
PARAMETER
tt
f(mclk)
Transition time, MCLK
MCLK frequency
MCLK jitter
Number of PCMCLK clock cycles per PCMSYN frame
tc(PCMCLK) PCMCLK clock period
Duty cycle, PCMCLK
tc(PCMSYN) PCMSYN clock period
Duty cycle, PCMCLK
transmit (128-kHz CLK) (see Figure 5)
PARAMETER
tsu(PCMSYN)
th(PCMSYN)
tv(PCMO)
Setup time, PCMSYN high before PCMCLK↑
Hold time, PCMSYN high after PCMCLK↓
Data valid time after the rising edge of PCMSYNC
receive (128-kHz CLK) (see Figure 4)
PARAMETER
tsu(PCSYN)
th(PCSYN)
tsu(PCMI)
th(PCMI)
Setup time, PCMSYN high before rising edge of PCMCLK
Hold time, PCMSYN high after falling edge of PCMCLK
Setup time, PCMI high or low before falling edge of PCMCLK
Hold time, PCMI high or low after falling edge of PCMCLK
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TLV320AIC1110
SLAS359 – DECEMBER 2001
MIN NOM
2.048
256
156
45%
488
50%
MAX
10
37%
256
512
68%
UNIT
ns
MHz
cycles
ns
MIN
MAX
UNIT
20 tc(PCMCLK)– 20
ns
20 tc(PCMCLK)– 20
MIN
MAX
UNIT
20 tc(PCMCLK)–20 ns
20 tc(PCMCLK)–20 ns
20
ns
20
ns
MIN NOM MAX
10
128
5%
16
16
742.19 781.25 820.31
40% 50% 60%
125
49.5% 50% 50.5%
UNIT
ns
kHz
ns
µs
MIN
MAX
UNIT
20 tc(PCMCLK)/4
ns
20 tc(PCMCLK)/4
50
ns
MIN
MAX
UNIT
20 tc(PCMCLK)/4
ns
20 tc(PCMCLK)/4
ns
20
ns
20
ns
17