OPA689M Datasheet, PDF (17/22 Pages) Texas Instruments – GAIN +4 STABLE WIDEBAND VOLTAGE-LIMITING AMPLIFIER

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OPA689M
GAIN +4 STABLE WIDEBAND
VOLTAGE-LIMITING AMPLIFIER
SGLS146B – MARCH 2003 – REVISED DECEMBER 2006
voltages can break down internal junctions, possibly leading to catastrophic failure. Single-supply operation is
possible as long as common mode voltage constraints are observed. The common mode input and output
voltage specifications can be interpreted as a required headroom to the supply voltage. Observing this input and
output headroom requirement will allow design of non-standard or single-supply operation circuits.Figure 31
shows one approach to single-supply operation.
ESD Protection
ESD damage has been known to damage MOSFET devices, but any semiconductor device is vulnerable to ESD
damage. This is particularly true for very high-speed, fine geometry processes.
ESD damage can cause subtle changes in amplifier input characteristics without necessarily destroying the
device. In precision operational amplifiers, this may cause a noticeable degradation of offset voltage and drift.
Therefore, ESD handling precautions are required when handling the OPA689.
Output Limiters
The output voltage is linearly dependent on the input(s) when it is between the limiter voltages V_H (pin 8) and V_L
(pin 5). When the output tries to exceed V_H or V_L, the corresponding limiter buffer takes control of the output
voltage and holds it at V_H or V_L.
Because the limiters act on the output, their accuracy does not change with gain. The transition from the linear
region of operation to output limiting is sharp—the desired output signal can safely come to within 30 mV of V_H
or V_L. Distortion performance is also good over the same range.
The limiter voltages can be set to within 0.7 V of the supplies (V_L≥– V_S + 0.7 V, V_H≤ +V_S– 0.7 V). They must
also be at least 400 mV apart (V_H– V_L≥ 0.4 V).
10 0
75
LIM ITER INPUT BIAS CUR R EN T vs BIAS VOLTAG E
M a x im u m O ve r T e m p e ra ture
50
25
M in im um O ve r Te m perature
0
− 25
− 50
− 75
L im ite r H e a d ro o m = + V _S − V _H
= V _L − (− V _S)
C u rre n t = I_VH or − I_VL
− 100
0 .0 0 .5 1 .0 1 .5 2 .0 2 .5 3 .0 3 .5 4 .0 4 .5 5 .0
L im ite r H e a d ro o m (V )
Figure 36. Limiter Bias Current vs Bias Voltage
When pins 5 and 8 are left open, V_H and V_L go to the Default Voltage Limit; the minimum values are in the
Specifications. Looking at Figure 37 for the zero bias current case will show the expected range of (V_S– default
limit voltages) = headroom.
When the limiter voltages are more than 2.1 V from the supplies (V_L≥– V_S + 2.1 V or V_H≤ V_S– 2.1 V), you can
use simple resistor dividers to set V_H and V_L (see Figure 30). Make sure you include the Limiter Input Bias
Currents (Figure 37) in the calculations (i.e., I_VL≥– 50 µA out of pin 5, and I_VH≤ 50 µA out of pin 8). For good
limiter voltage accuracy, run at least 1-mA quiescent bias current through these resistors.
When the limiter voltages need to be within 2.1 V of the supplies (V_L≤– V_S + 2.1 V or V_H≥ V_S– 2.1 V), consider
using low impedance buffers to set V_H and V_L to minimize errors due to bias current uncertainty. This will
typically be the case for single supply operation (V_S = 5 V). Figure 31 runs 2.5 mA through the resistive divider
that sets V_H and V_L. This keeps errors due to I_VH and I_VL <±1% of the target limit voltages.
The limiters' DC accuracy depends on attention to detail. The two dominant error sources can be improved as
follows:
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