LMR22007 Datasheet, PDF (17/24 Pages) Texas Instruments – LMR22007 2.7V - 20V, 750mA Step-Down Converter with Adjustable Input Current Limit

LMR22007
www.ti.com
SNVS985A – OCTOBER 2013 – REVISED OCTOBER 2013
T_BA

T_J-MAX  T_A-MAX
P_{IC_LOSS}
 <_JB
(12)
The typical thermal impedance from junction to board is 32.5°C/W. Use the power dissipation curves in the
Typical Performance Characteristics section to estimate the P_IC-LOSS for the application being designed. In this
application it is around 0.4W
T_BA

125qC  85qC
0.4 W
 32.5 ^qC
W

67.5 ^qC
W
(13)
To reach θ_BA = 67.5°C/W, the PCB is required to dissipate heat effectively. With no airflow and no external heat-
sink, a good estimate of the required board area covered by 2 oz. copper on both the top and bottom metal
layers is:
Board Area_cm² J ⁵⁰⁰ b ^{GC K cm2}
6_CA
W
(14)
As a result, approximately 7.4 square cm of 2 oz copper on top and bottom layers is the minimum required area
for the example PCB design. This is 2.72 x 2.72 cm (1.07 x 1.07 in). The GND, and V_IN pins should be
connected to as large a copper plane as possible to remove heat from the device.
For an example of a high thermal performance PCB layout refer to AN-2020 and the evaluation board
documentation.
LAYOUT HIGHLIGHTS
1. Minimize area of switched current loops. From an EMI reduction standpoint, it is imperative to minimize the
high di/dt paths during PC board layout as shown in the figure above. The high current loops that do not
overlap have high di/dt content that will cause observable high frequency noise on the output pin if the input
capacitor CIN is placed at a distance away from the LMR22007. Therefore place C_IN as close as possible to
the LMR22007 V_IN and PGND pins. This will minimize the high di/dt area and reduce radiated EMI.
Additionally, grounding for both the input and output capacitor should consist of a localized top side plane
that connects to the PGND pin.
2. Have a single point ground. The ground connections for the feedback, and enable components should be
routed to the GND pin of the device. This prevents any switched or load currents from flowing in the analog
ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output
voltage ripple behavior.
3. Minimize trace length to the FB pin. Both feedback resistors, R_FBT and R_FBB should be located close to the
FB pin. Since the FB node is high impedance, maintain the copper area as small as possible. The traces
from R_FBT, R_FBB should be routed away from the body of the LMR22007 to minimize possible noise pickup.
4. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or
output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a
separate feedback voltage sense trace is made to the load. Doing so will correct for voltage drops and
provide optimum output accuracy.
5. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the GND pin to the
ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be
connected to inner layer heat-spreading ground planes. For best results use 0.2 to 0.3mm thermal vias
spaced at 1mm. Ensure enough copper area is used for heat-sinking to keep the junction temperature below
125°C.
Copyright © 2013, Texas Instruments Incorporated
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