INA220-Q1 Datasheet, PDF (17/38 Pages) Texas Instruments – Automotive Grade, 26-V, Bi-Directional, Zero-Drift, Low- or High-Side, I2C-Compatible Current/Power Monitor

www.ti.com
INA220-Q1
SLOS785B – JUNE 2012 – REVISED MARCH 2016
8.5.5.1 High-Speed Mode
When the bus is idle, both the SDA and SCL lines are pulled high by the pullup devices. The master generates a
start condition followed by a valid serial byte containing high-speed (HS) master code 00001XXX. This
transmission is made in fast (400 kbps) or standard (100 kbps) (F/S) mode at no more than 400 kbps. The
INA220-Q1 does not acknowledge the HS master code, but does recognize it and switches its internal filters to
support 2.56-Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission
speeds up to 2.56 Mbps are allowed. Instead of using a stop condition, repeated start conditions should be used
to secure the bus in HS-mode. A STOP condition ends the HS-mode and switches all the internal filters of the
INA220-Q1 to support the F/S mode. See Table 2 and Figure 18 for timing.
Table 2. Bus Timing Diagram Definitions⁽¹⁾
FAST MODE
MIN
MAX
HIGH-SPEED MODE
MIN
MAX
UNIT
ƒ_(SCL)
t_(BUF)
SCL operating frequency
Bus free time between STOP and START
condition
0.001
1300
0.4
0.001
160
2.56
MHz
ns
t_(HDSTA)
Hold time after repeated START condition
After this period, the first clock is generated.
600
160
ns
t_(SUSTA)
t_(SUSTO)
t_(HDDAT)
t_(SUDAT)
t_(LOW)
t_(HIGH)
t_FDA
t_FCL
t_RCL
t_RCL
Repeated START condition setup time
STOP condition setup time
Data hold time
Data setup time
SCL clock LOW period
SCL clock HIGH period
Data fall time
Clock fall time
Clock rise time
Clock rise time for SCLK ≤ 100 kHz
600
160
ns
600
160
ns
0
900
0
90
ns
100
10
ns
1300
250
ns
600
60
ns
300
150
ns
300
40
ns
300
40
ns
1000
ns
(1) Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not production tested.
Condition: A0=A1=0.
t_(LOW)
t_R
t_F
t_(HDSTA)
SCL
t_(HDSTA)
SDA
t_(BUF)
P
S
t_(HIGH)
t_(HDDAT)
t_(SUSTA)
t_(SUDAT)
S
Figure 18. Bus Timing Diagram
t_(SUSTO)
P
8.5.5.2 Power-Up Conditions
Power-up conditions apply to a software reset through the RST bit (bit 15) in the Configuration register, or the I²C
bus General Call Reset.
Copyright © 2012–2016, Texas Instruments Incorporated
Product Folder Links: INA220-Q1
Submit Documentation Feedback
17