DS90CR483A Datasheet, PDF (17/26 Pages) Texas Instruments – DS90CR483A/DS90CR484A 48-Bit LVDS Channel Link SER/DES 33-112 MHz

can be implemented in case pre-emphasis is needed to coun-
teract heavy capacitive loading effects.
HOW TO CONFIGURE FOR CABLE INTERCONNECT
APPLICATIONS
In applications that require the long cable drive capability. The
DS90CR483A/DS90CR484A chipset is improved over prior
generations of Channel Link devices and offers higher band-
width support and longer cable drive with the use of DC
balanced data transmission, pre-emphasis. Cable drive is en-
hanced with a user selectable pre-emphasis feature that pro-
vides additional output current during transitions to counteract
cable loading effects. This requires the use of one pull up re-
sistor to Vcc; please refer to to set the level needed. Optional
DC balancing on a cycle-to-cycle basis, is also provided to
reduce ISI (Inter-Symbol Interference) for long cable applica-
tions. With pre-emphasis and DC balancing, a low distortion
eye-pattern is provided at the receiver end of the cable. These
enhancements allow cables 5+ meters in length to be driven.
Depending upon clock rate and the media being driven, the
cable Deskew feature may also be employed - see discussion
on DESKEW, RSKM and RSKMD above.
SUPPLY BYPASS RECOMMENDATIONS
Bypass capacitors must be used on the power supply pins.
Different pins supply different portions of the circuit, therefore
capacitors should be nearby all power supply pins except as
noted in the pin description table. Use high frequency ceramic
(surface mount recommended) 0.1µF capacitors close to
each supply pin. If space allows, a 0.01µF capacitor should
be used in parallel, with the smallest value closest to the de-
vice pin. Additional scattered capacitors over the printed cir-
cuit board will improve decoupling. Multiple (large) via should
be used to connect the decoupling capacitors to the power
plane. A 4.7 to 10 µF bulk cap is recommended near the
PLLVCC pins and also the LVDSVCC (pin #40) on the Trans-
mitter. Connections between the caps and the pin should use
wide traces.
INPUT SIGNAL QUALITY REQUIREMENTS -
TRANSMITTER
The input signal quality must comply to the datasheet re-
quirements, please refer to the "Recommended Transmitter
Input Characteristics" table for specifications. In addition un-
dershoots in excess of the ABS MAX specifications are not
recommended. If the line between the host device and the
transmitter is long and acts as a transmission line, then ter-
mination should be employed. If the transmitter is being driven
from a device with programmable drive strengths, data inputs
are recommended to be set to a weak setting to prevent
transmission line effects. The clock signal is typically set high-
er to provide a clean edge that is also low jitter.
UNUSED LVDS OUTPUTS
Unused LVDS output channels should be terminated with 100
Ohm at the transmitter’s output pin.
RECEIVER OUTPUT DRIVE STRENGTH
The DS90CR484A output specify a 8pF load, V_OH and V_OL
are tested at ± 2mA, which is intended for only 1 or maybe 2
loads. If high fan-out is required or long transmission line driv-
ing capability, buffering the receiver output is recommended.
Receiver outputs do not support / provide a TRI-STATE func-
tion.
LVDS INTERCONNECT GUIDELINES
See AN-1108 and AN-905 for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
— S = space between the pair
— 2S = space between pairs
— 3S = space to TTL signal
• Minimize the number of VIA
• Use differential connectors when operating above
500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Minimize skew between pairs
• Terminate as close to the RXinputs as possible
FOR MORE INFORMATION
Channel Link Applications Notes currently available:
• AN-1041 Introduction to Channel Link
• AN-1059 RSKM Calculations
• AN-1108 PCB and Interconnect Guidelines
• AN-905 Differential Impedance
• National’s LVDS Owner’s Manual
www.national.com
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