DRV8824_16 Datasheet, PDF (17/35 Pages) Texas Instruments – Stepper Motor Controller IC

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DRV8824
SLVSA06J – OCTOBER 2009 – REVISED JULY 2014
8.3.6 nRESET, nENBLE and nSLEEP Operation
The nRESET pin, when driven active low, resets internal logic, and resets the step table to the home position. It
also disables the H-bridge drivers. The STEP input is ignored while nRESET is active.
The nENBL pin is used to control the output drivers and enable or disable operation of the indexer. When nENBL
is low, the output H-bridges are enabled, and rising edges on the STEP pin are recognized. When nENBL is
high, the H-bridges are disabled, the outputs are in a high-impedance state, and the STEP input is ignored.
Driving nSLEEP low puts the device into a low-power sleep state. In this state, the H-bridges are disabled, the
gate drive charge pump is stopped, the V3P3OUT regulator is disabled, and all internal clocks are stopped. In
this state, all inputs are ignored until nSLEEP returns high. When returning from sleep mode, some time
(approximately 1 ms) needs to pass before applying a STEP input, to allow the internal circuitry to stabilize.
The nRESET and nENABLE pins have internal pulldown resistors of 100 kΩ. The nSLEEP pin has an internal
pulldown resistor of 1 MΩ.
8.3.7 Protection Circuits
The DRV8824 is fully protected against undervoltage, overcurrent, and overtemperature events.
8.3.7.1 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled and the
nFAULT pin will be driven low. The device remains disabled until either nRESET pin is applied, or VMx is
removed and re-applied.
Overcurrent conditions on both high and low side devices, that is, a short to ground, supply, or across the motor
winding, all result in an overcurrent shutdown. Note that overcurrent protection does not use the current sense
circuitry used for PWM current control, and is independent of the I_SENSE resistor value or xVREF voltage.
8.3.7.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be
driven low. After the die temperature has fallen to a safe level, operation automatically resumes.
8.3.7.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VMx pins falls below the UVLO threshold voltage, all circuitry in the device will
be disabled and internal logic will be reset. Operation resumes when V_(VMx) rises above the UVLO threshold.
8.3.8 Thermal Information
8.3.8.1 Thermal Protection
The DRV8824 has TSD, as described in Thermal Shutdown (TSD). If the die temperature exceeds approximately
150°C, the device is disabled until the temperature drops to a safe level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
8.3.8.2 Power Dissipation
Power dissipation in the DRV8824 is dominated by the power dissipated in the output FET resistance, or R_DS(ON).
Average power dissipation when running a stepper motor can be roughly estimated by Equation 2.
 ²
P_TOT 4 u R_DS(ON) u I_OUT(RMS)
where
• P_TOT is the total power dissipation
• R_DS(ON) is the resistance of each FET
• I_OUT(RMS) is the RMS output current being applied to each winding
(2)
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