DAC7632VFTG4 Datasheet, PDF (17/26 Pages) Texas Instruments – 16-Bit, Dual Voltage Output

SERIAL DATA INPUT
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
DACSEL
X
QUICK
LOAD
X
X
X
X
X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DACSEL
CS
0
L
1
L
X
H
X
H
X
X
X
X
RST
H
H
H
H
↑
↑
RSTSEL
X
X
X
X
L
H
TABLE I. DAC7632 Logic Truth Table.
LDAC
X
X
↑
H
X
X
LOAD
L
L
H
H
X
X
INPUT
REGISTER
Write
Write
Hold
Hold
Reset to 0000_H
Reset to 8000_H
DAC
REGISTER
Hold
Hold
Write
Hold
Reset to 0000_H
Reset to 8000_H
MODE
Write Input
Write Input
Update
Hold
Reset to Zero-Scale
Reset to Mid-scale
DAC
A
B
All
All
All
All
Data presented to SDI is clocked into the shift register on
each rising CLK edge. This data is latched into the input
register(s) via a logic-low level on LOAD. The data is directed
from the shift register to the desired input register(s) specified
by data bits 21 and 23. The internal DAC registers are edge
triggered and not level triggered. When the LDAC signal is
transitioned from LOW to HIGH, the digital word currently in
the input registers are latched. This double-buffered architec-
ture has been designed so that new data can be entered for
each DAC without disturbing the analog outputs. When the
new data has been entered into the device, both DAC
outputs can be updated simultaneously by the rising edge of
LDAC. Additionally, it allows the input registers to be written
to at any point, then the DAC output voltages can be
synchronously changed via a trigger signal (LDAC).
Note that CS and CLK are combined with an OR gate, which
controls the serial-to-parallel shift register. These two inputs
are completely interchangeable. In addition, care must be
taken with the state of CLK when CS rises at the end of a
serial transfer. If CLK is LOW when CS rises, the OR gate
will provide a rising edge to the shift register, shifting the
internal data one additional bit. The result will be incorrect
data and possible selection of the wrong input register(s). If
both CS and CLK are used, CS should rise only when CLK
is HIGH. If not, then either CS or CLK can be used to operate
the shift register (the remaining pin should be tied to DGND).
Please refer to Table II for more information.
CS⁽¹⁾
CLK⁽¹⁾
LOAD
RST SERIAL SHIFT REGISTER
H⁽²⁾
X⁽³⁾
H
H
L⁽⁴⁾
L
H
H
L
↑⁽⁵⁾
H
H
↑
L
H
H
H⁽⁶⁾
X
L⁽⁷⁾
H
H⁽⁶⁾
X
H
↑⁽⁸⁾
No Change
No Change
Advanced One Bit
Advanced One Bit
No Change
No Change
NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH.
(3) X = Don’t Care. (4) L = Logic LOW. (5) = Positive Logic Transition.
(6) A HIGH value is suggested in order to avoid a “false clock” from
advancing the shift register and changing the shift register. (7) If data is
clocked into the serial register while LOAD is LOW, the input registers will
change as data flows through the shift register. This will corrupt the data
in each DAC register that has been erroneously selected. (8) Rising edge
of RST causes no change in the contents of the serial shift register.
TABLE II. Serial Shift Register Truth Table.
SERIAL-DATA OUTPUT
The Serial-Data Output pin (SDO) is the internal shift register’s
output. For the DAC7632, SDO is a driven output and does
not require an external pull-up. Any number of DAC7632s
can be daisy-chained by connecting the SDO pin of one
device to the SDI pin of the following device in the chain, as
shown in Figure 14.
SCK
DIN
CS
DAC7632
CLK
SDI SDO
CS
DAC7632
CLK
SDI
SDO
CS
DAC7632
CLK
SDI SDO
CS
To
Other
Serial
Devices
FIGURE 14. Daisy-Chaining Multiple DAC7632s.
DAC7632
17
SBAS234A
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