ADS7841-Q1 Datasheet, PDF (17/24 Pages) Texas Instruments – 12-BIT 4-CHANNEL SERIAL-OUTPUT SAMPLING ANALOG-TO-DIGITAL CONVERTER

ADS7841-Q1
www.ti.com
SBAS469B – MARCH 2009 – REVISED SEPTEMBER 2011
Operating the ADS7841 in auto power-down mode results in the lowest power dissipation, and there is no
conversion time "penalty" on power-up. The very first conversion is valid. SHDN can be used to force an
immediate power-down.
PCB Layout
For optimum performance, care should be taken with the physical layout of the ADS7841 circuitry. This is
particularly true if the reference voltage is low and/or the conversion rate is high.
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground
connections, and digital inputs that occur just prior to latching the output of the analog comparator. Thus, during
any single conversion for an n-bit SAR converter, there are n "windows" in which large external transient voltages
can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby
digital logic, and high power devices. The degree of error in the digital output depends on the reference voltage,
layout, and the exact timing of the external event. The error can change if the external event changes in time
with respect to the DCLK input.
With this in mind, power to the ADS7841 should be clean and well bypassed. A 0.1-μF ceramic bypass capacitor
should be placed as close to the device as possible. In addition, a 1-μF to 10-μF capacitor and a 5Ω or 10Ω
series resistor may be used to low-pass filter a noisy supply.
The reference should be similarly bypassed with a 0.1-μF capacitor. Again, a series resistor and large capacitor
can be used to low-pass filter the reference voltage. If the reference voltage originates from an op amp, make
sure that it can drive the bypass capacitor without oscillation (the series resistor can help in this case). The
ADS7841 draws very little current from the reference on average, but it does place larger demands on the
reference circuitry over short periods of time (on each rising edge of DCLK during a conversion).
The ADS7841 architecture offers no inherent rejection of noise or voltage variation in regards to the reference
input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple
from the supply appears directly in the digital results. While high-frequency noise can be filtered out as discussed
in the previous paragraph, voltage variation due to line frequency (50 Hz or 60 Hz) can be difficult to remove.
The GND pin should be connected to a clean ground point. In many cases, this is the "analog" ground. Avoid
connections that are too near the grounding point of a microcontroller or digital signal processor. If needed, run a
ground trace directly from the converter to the power supply entry point. The ideal layout includes an analog
ground plane dedicated to the converter and associated analog circuitry.
Copyright © 2009–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS7841-Q1
Submit Documentation Feedback
17