ADC34J2X Datasheet, PDF (17/88 Pages) Texas Instruments – The ADC34J2x are a high-linearity

www.ti.com
ADC34J22, ADC34J23, ADC34J24, ADC34J25
SBAS669A – MAY 2014 – REVISED JANUARY 2015
7.14 Timing Characteristics
Typical values are at 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. Minimum and
maximum values are across the full temperature range: T_MIN = –40°C to T_MAX = 85°C. See Figure 143.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SAMPLE TIMING CHARACTERISTICS
Aperture delay
0.85
1.25
1.65
ns
Aperture delay matching
Between two channels on the same device
Between two devices at the same temperature and supply
voltage
±70
ps
±150
ps
Aperture jitter
Wake-up time
Time to valid data after coming out of STANDBY mode
Time to valid data after coming out of global power-down
200
f_S rms
35
100
µs
85
300
µs
t_{SU_SYNC~}
Setup time for SYNC~
Referenced to input clock rising edge
1
ns
t_{H_SYNC~}
Hold time for SYNC~
Referenced to input clock rising edge
100
ps
t_{SU_SYSREF} Setup time for SYSREF Referenced to input clock rising edge
1
ns
t_{H_SYSREF}
Hold time for SYSREF
Referenced to input clock rising edge
100
ps
CML OUTPUT TIMING CHARACTERISTICS
Unit interval
312.5
1667
ps
Serial output data rate
3.2 Gbps
t_R, t_F
Total jitter
Data rise time,
data fall time
3.125 Gbps (20x mode, f_S = 156.25 MSPS)
Rise and fall times measured from 20% to 80%,
differential output waveform,
600 Mbps ≤ bit rate ≤ 3.125 Gbps
0.3
P-P^UI
105
ps
Table 2. Latency in Different Modes⁽¹⁾⁽²⁾
MODE
20x
40x
PARAMETER
ADC latency
Normal OVR latency
Fast OVR latency
From SYNC~ falling edge to CGS phase⁽³⁾
From SYNC~ rising edge to ILA sequence⁽⁴⁾
ADC latency
Normal OVR latency
Fast OVR latency
From SYNC~ falling edge to CGS phase⁽³⁾
From SYNC~ rising edge to ILA sequence⁽⁴⁾
LATENCY (N Cycles)
17
9
7
15
17
16
9
7
14
12
TYPICAL DATA DELAY (t_D, ns)
0.29 × t_S + 3
0.5 × t_S + 2
0.5 × t_S + 2
0.3 × t_S + 4
0.3 × t_S + 4
0.85 × t_S + 3.9
0.5 × t_S + 2
0.5 × t_S + 2
0.9 × t_S + 4
0.9 × t_S + 4
(1) Overall latency = latency + t_D.
(2) t_S is the time period of the ADC conversion clock.
(3) Latency is specified for subclass 2. In subclass 0, the SYNC~ falling edge to CGS phase latency is 16 clock cycles in 10x mode and 15
clock cycles in 20x mode.
(4) Latency is specified for subclass 2. In subclass 0, the SYNC~ rising edge to ILA sequence latency is 11 clock cycles in 10x mode and
11 clock cycles in 20x mode.
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: ADC34J22 ADC34J23 ADC34J24 ADC34J25