AM3359_17 Datasheet, PDF (167/253 Pages) Texas Instruments – Sitara Processors

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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
SPRS717J – OCTOBER 2011 – REVISED APRIL 2016
7.7.2.2.2.9 DDR2 Signal Termination
Signal terminations are required on the CK and ADDR_CTRL net class signals. Serial terminations should
be used on the CK and ADDR_CTRL lines and is the preferred termination scheme. On-device
terminations (ODTs) are required on the DQS[x] and DQ[x] net class signals. They should be enabled to
ensure signal integrity. Table 7-52 shows the specifications for the series terminators. Placement of serial
terminations for ADDR_CTRL net class signals should be close to the AM335x device.
Table 7-52. DDR2 Signal Terminations
NO.
PARAMETER
MIN
1 CK net class⁽¹⁾
0
2 ADDR_CTRL net class^(1)(2)(3)
0
3 DQS0, DQS1, DQ0, and DQ1 net classes⁽⁵⁾
N/A
(1) Only series termination is permitted.
(2) Series termination values larger than typical only recommended to address EMI issues.
(3) Series termination values should be uniform across net class.
(4) Zo is the DDR2 PCB trace characteristic impedance.
(5) No external termination resistors are allowed and ODT must be used for these net classes.
TYP
22
MAX
10
Zo⁽⁴⁾
N/A
UNIT
Ω
Ω
Ω
If the DDR2 interface is operated at a lower frequency (<200-MHz clock rate), on-device terminations are
not specifically required for the DQS[x] and DQ[x] net class signals and serial terminations for the CK and
ADDR_CTRL net class signals are not mandatory. System designers may evaluate the need for serial
terminators for EMI and overshoot reduction. Placement of serial terminations for DQS[x] and DQ[x] net
class signals should be determined based on PCB analysis. Placement of serial terminations for
ADDR_CTRL net class signals should be close to the AM335x device. Table 7-53 shows the
specifications for the serial terminators in such cases.
Table 7-53. Lower-Frequency DDR2 Signal Terminations
NO. PARAMETER
1 CK net class⁽¹⁾
2 ADDR_CTRL net class^(1)(3)(4)
MIN
TYP
0
22
0
22
3 DQS0, DQS1, DQ0, and DQ1 net classes
0
22
(1) Only series termination is permitted.
(2) Zo is the DDR2 PCB trace characteristic impedance.
(3) Series termination values larger than typical only recommended to address EMI issues.
(4) Series termination values should be uniform across net class.
MAX
Zo⁽²⁾
Zo⁽²⁾
Zo⁽²⁾
UNIT
Ω
Ω
Ω
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Peripheral Information and Timings 167
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