TMS320C6745_16 Datasheet, PDF (161/227 Pages) Texas Instruments – Fixed- and Floating-Point Digital Signal Processor

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TMS320C6745, TMS320C6747
SPRS377F – SEPTEMBER 2008 – REVISED JUNE 2014
6.21.1 LCD Interface Display Driver (LIDD Mode)
No.
16 t_{su(LCD_D)}
17 t_{h(LCD_D)}
Table 6-82. LCD LIDD Mode Timing Requirements
PARAMETER
Setup time, LCD_D[15:0] valid before LCD_MCLK high
Hold time, LCD_D[15:0] valid after LCD_MCLK high
MIN MAX UNIT
7
ns
0.5
ns
No.
4
5
6
7
8
9
10
11
12
13
14
15
t_{d(LCD_D_V)}
t_{d(LCD_D_I)}
t_{d(LCD_E_A})
t_{d(LCD_E_I)}
t_{d(LCD_A_A)}
t_{d(LCD_A_I)}
t_{d(LCD_W_A)}
t_{d(LCD_W_I)}
t_{d(LCD_STRB_A)}
t_{d(LCD_STRB_I)}
t_{d(LCD_D_Z)}
t_{d(Z_LCD_D)}
1
2
3
LCD_MCLK
LCD_D[15:0]
LCD_PCLK
LCD_VSYNC
LCD_HSYNC
LCD_AC_ENB_CS
Table 6-83. LCD LIDD Mode Timing Characteristics
PARAMETER
Delay time, LCD_MCLK high to LCD_D[15:0] valid (write)
Delay time, LCD_MCLK high to LCD_D[15:0] invalid (write)
Delay time, LCD_MCLK high to LCD_AC_ENB_CS low
Delay time, LCD_MCLK high to LCD_AC_ENB_CS high
Delay time, LCD_MCLK high to LCD_VSYNC low
Delay time, LCD_MCLK high to LCD_VSYNC high
Delay time, LCD_MCLK high to LCD_HSYNC low
Delay time, LCD_MCLK high to LCD_HSYNC high
Delay time, LCD_MCLK high to LCD_PCLK active
Delay time, LCD_MCLK high to LCD_PCLK inactive
Delay time, LCD_MCLK high to LCD_D[15:0] in 3-state
Delay time, LCD_MCLK high to LCD_D[15:0] (valid from 3-state)
MIN MAX UNIT
-0.5 10
ns
-0.5 10
ns
-0.5
7
ns
-0.5
7
ns
-0.5
8
ns
-0.5
8
ns
-0.5
8
ns
-0.5
8
ns
-0.5 12
ns
-0.5 12
ns
-0.5 12
ns
-0.5 12
ns
W_SU
(0 to 31)
W_STROBE
(1 to 63)
CS_DELAY
W_HOLD
(1 to 15)
R_SU
(0 to 31)
R_STROBE
(1 to 63)
R_HOLD
(1 to 15)
CS_DELAY
4
Write Data
10
12
5
11
13
14
17
16
Read Status
8
12
13
15
Data[7:0]
Not Used
9
RS
R/W
E0
E1
Figure 6-47. Character Display HD44780 Write
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Peripheral Information and Electrical Specifications 161
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