TLV320DAC3100 Datasheet, PDF (16/98 Pages) Texas Instruments – Low-Power Stereo Audio DAC With Audio Processing and Mono Class-D Speaker Amplifier

TLV320DAC3100
SLAS671A – FEBRUARY 2010 – REVISED MAY 2012
www.ti.com
• Digital sine-wave generator for clicks and beeps
• Stereo headphone/lineout amplifier
• Class-D mono amplifier capable of driving 4-Ω speakers
• Pin-controlled or register-controlled volume level
• Power-down de-pop and power-up soft start
• Analog inputs
• I²C control interface
• Power-down control block
Following a toggle of the RESET pin or a software reset, the device operates in the default mode. The I²C
interface is used to write to the control registers to configure the device.
The I²C address assigned to the TLV320DAC3100 is 001 1000. This device always operates in an I²C
slave mode. All registers are 8-bit, and all writable registers have read-back capability. The device auto-
increments to support sequential addressing and can be used with I²C fast mode. Once the device is
reset, all appropriate registers are updated by the host processor to configure the device as needed by the
user.
5.2.1 Device Initialization
5.2.1.1 Reset
The TLV320DAC3100 internal logic must be initialized to a known condition for proper device function. To
initialize the device to its default operating condition, the hardware reset pin (RESET) must be pulled low
for at least 10 ns. For this initialization to work, both the IOVDD and DVDD supplies must be powered up.
It is recommended that while the DVDD supply is being powered up, the RESET pin be pulled low.
The device can also be reset via software reset. Writing a 1 into page 0 / register 1, bit D0 resets the
device.
5.2.1.2 Device Start-Up Lockout Times
After the TLV320DAC3100 is initialized through hardware reset at power up or software reset, the internal
memories are initialized to default values. This initialization takes place within 1 ms after pulling the
RESETsignal high. During this initialization phase, no register-read or register-write operation should be
performed on DAC coefficient buffers. Also, no block within the codec should be powered up during the
initialization phase.
5.2.1.3 PLL Start-Up
Whenever the PLL is powered up, a start-up delay of approximately of 10 ms occurs after the power-up
command of the PLL and before the clocks are available to the codec. This delay is to ensure stable
operation of the PLL and clock-divider logic.
5.2.1.4 Power-Stage Reset
The power-stage-only reset is used to reset the device after an overcurrent latching shutdown has
occurred. Using this reset re-enables the output stage without resetting all of the registers in the device.
Each of the four power stages has its own dedicated reset bit. The headphone power-stage reset is
performed by setting page 1/ register 31, bit D7 for HPL and by setting page 1 / register 31, bit D6 for
HPR. The speaker power-stage reset is performed by setting page 1 / register 32, bit D7 for SPKP and
SPKM.
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APPLICATION INFORMATION
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