THS1401_15 Datasheet, PDF (16/28 Pages) Texas Instruments – 14-BIT, 1/3/8 MSPS, DSP-COMPATIBLE ANALOG-TO-DIGITAL

THS1401
THS1403
THS1408
SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005
PRINCIPLES OF OPERATION
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Table 4. Control Register, Address 3, Read
BIT
D13
Function PWD
D12
REF
D11
FOR
D10
TM2
D9
TM1
D8
TM0
D7
OFF
D6
RES
D5
RES
D4
RES
D3
RES
D2
RES
D1
RES
D0
RES
Table 5. Control Register, Address 3, Write
BIT
Function
Default
D13
PWD
0
D12
REF
0
D11
FOR
0
D10
TM2
0
D9
TM1
0
D8
TM0
0
D7
OFF
0
D6
RES
0
D5
RES
0
D4
RES
0
D3
RES
0
D2
RES
0
D1
RES
0
D0
RES
0
PWD:
REF:
FOR:
TM2−0:
Power down
Reference select
Output format
Test mode
OF:
RES
Offset correction
Reserved
0 = normal operation
1 = power down
0 = internal reference 1 = external reference
0 = straight binary
1 = 2s complement
000 = normal operation
001 = both inputs = REF−
010 = IN+ at V_CM (Voltage at CML pin), IN− at REF−
011 = IN+ at REF+, IN− at REF−
100 = normal operation
101 = both inputs = REF+
110 = IN+ at REF−, IN− at V_CM (Voltage at CML pin)
111 = IN+ at REF−, IN− at REF+
0 = enable
1 = disable
Must be set to 0.
APPLICATION INFORMATION
driving the analog input
The THS1401/3/8 ADCs have a fully differential input. A differential input is advantageous with respect to SNR,
SFDR, and THD performance because the signal peak-to-peak level is 50% of a comparable single-ended
input.
There are three basic input configurations:
D Fully differential
D Transformer coupled single-ended to differential
D Single-ended
fully differential configuration
In this configuration, the ADC converts the difference (∆IN) of the two input signals on IN+ and IN−.
22 Ω
100 pF
IN+
22 Ω
100 pF
THS1401/3/8
IN−
Figure 19. Differential Input
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