SM320C50-EP Datasheet, PDF (16/29 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SM320C50ĆEP
DIGITAL SIGNAL PROCESSOR
SGUS040A − AUGUST 2002 − REVISED JANUARY 2006
READY TIMING FOR EXTERNALLY GENERATED WAIT STATES
timing requirements [H = 0.5t_c(CO)] (see Figure 9 and Figure 10)
tsu(RY-COH)
th(CO-RYH)
tsu(RY-RDL)
th(RDL-RY)
tv(WEL-RY)
th(WEL-RY)
Setup time, READY before CLKOUT1 rises
Hold time, READY after CLKOUT1 rises
Setup time, READY before RD falls
Hold time, READY after RD falls
Valid time, READY after WE falls
Hold time, READY after WE falls
MIN
10
0
10
0
H − 15
H+5
MAX
UNIT
ns
ns
ns
ns
ns
ns
CLKOUT1
tsu(RY-COH)
ADDRESS
READY
tsu(RY-RDL)
th(RDL-RY)
RD
th(CO-RYH)
Wait State
Generated
Internally
Wait State
Generated
by READY
Figure 9. Ready Timing for Externally Generated Wait States During an External Read Cycle
CLKOUT1
ADDRESS
READY
WE
tsu(RY-COH)
tv(WEL-RY)
th(CO-RYH)
th(WEL-RY)
Wait State Generated by READY
Figure 10. Ready Timing for Externally Generated Wait States During an External Write Cycle
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