PCA9539_15 Datasheet, PDF (16/42 Pages) Texas Instruments – SMBus Low-Power I/O Expander

PCA9539
SCPS130G – AUGUST 2005 – REVISED JUNE 2014
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8.2 Device Functional Modes
8.2.1 RESET Input
A reset can be accomplished by holding the RESET pin low for a minimum of t_W. The PCA9539 registers and
I²C/SMBus state machine are held in their default states until RESET is once again high. This input requires a
pullup resistor to V_CC, if no active connection is used.
8.2.1.1 RESET Errata
If RESET voltage set higher than VCC, current will flow from RESET pin to VCC pin.
System Impact
VCC will be pulled above its regular voltage level
System Workaround
Design such that RESET voltage is same or lower than VCC
8.2.2 Power-On Reset
When power (from 0 V) is applied to V_CC, an internal power-on reset holds the PCA9539 in a reset condition until
V_CC has reached V_POR. At that point, the reset condition is released and the PCA9539 registers and I²C/SMBus
state machine initialize to their default states. After that, V_CC must be lowered to below 0.2 V and then back up to
the operating voltage for a power-reset cycle.
Refer to the Power-On Reset Errata section.
8.2.3 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 (in Figure 18) are off, which creates a high-impedance
input. The input voltage may be raised above V_CC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register. In
this case, there are low-impedance paths between the I/O pin and either V_CC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
8.2.4 Interrupt (INT) Output
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, t_iv, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting, data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal.
Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of
the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an
interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin
does not match the contents of the Input Port register. Because each 8-pin port is read independently, the
interrupt caused by port 0 is not cleared by a read of port 1 or vice versa.
The INT output has an open-drain structure and requires pullup resistor to V_CC.
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