LP5523_16 Datasheet, PDF (16/56 Pages) Texas Instruments – LP5523 Programmable 9-Output LED Driver

LP5523
SNVS550D – SEPTEMBER 2009 – REVISED MAY 2013
www.ti.com
Data Validity
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of
the data line can only be changed when clock signal is LOW.
SCL
SDA
data
change
allowed
data
valid
data
change
allowed
data
valid
data
change
allowed
Figure 20. Data Validity Diagram
Start and Stop Conditions
START and STOP conditions classify the beginning and the end of the data transfer session. A START condition
is defined as the SDA signal transitioning from HIGH to LOW while SCL line is HIGH. A STOP condition is
defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The bus master always generates
START and STOP conditions. The bus is considered to be busy after a START condition and free after a STOP
condition. During data transmission, the bus master can generate repeated START conditions. First START and
repeated START conditions are equivalent, function-wise.
Transferring Data
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP5523 pulls
down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP5523 generates an
acknowledge after each byte has been received.
There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must
indicate to the transmitter an end of data by not acknowledging (“negative acknowledge”) the last byte clocked
out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the
master), but the SDA line is not pulled down.
After the START condition, the bus master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (READ or WRITE). The LP5523 address is defined with ASEL0 and ASEL1
pins, and it is 32h when ASEL1 and ASEL0 are connected to GND. For the eighth bit, a “0” indicates a WRITE
and a “1” indicates a READ. The second byte selects the register to which the data will be written. The third byte
contains data to write to the selected register.
I²C-Compatible Chip Address
ASEL0 and ASEL1 pins configure the chip address for the LP5523 as shown in Table 1.
ASEL1
GND
GND
VEN
VEN
Table 1. LP5523 Chip Address Configuration
ASEL0
GND
VEN
GND
VEN
ADDRESS
(HEX)
32
33
34
35
8-BIT HEX ADDRESS
WRITE/READ
64/65
66/67
68/69
6A/6B
16
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