LM3475 Datasheet, PDF (16/25 Pages) National Semiconductor (TI) – Hysteretic PFET Buck Controller

LM3475
SNVS239C – OCTOBER 2004 – REVISED OCTOBER 2015
8.2.3 Application Curves
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Figure 14. Load Transient Response with External Ramp
(Circuit from Figure 12)
Figure 15. Load Transient Response
(Typical Application Circuit from Figure 16)
9 Power Supply Recommendations
The LM3475 controller is designed to operate from various DC power supplies. VIN input should be protected
from reversal voltage and voltage dump over 16 volts. The impedance of the input supply rail should be low
enough that the input current transient does not cause drop below VIN UVLO level. If the input supply is
connected by using long wires, additional bulk capacitance may be required in addition to normal input capacitor.
10 Layout
10.1 Layout Guidelines
PC board layout is very important in all switching regulator designs. Poor layout can cause EMI problems, excess
switching noise and poor operation.
As shown in Figure 16, place the ground of the input capacitor as close as possible to the anode of the diode.
This path also carries a large AC current. The switch node, the node connecting the diode cathode, inductor, and
PFET drain, should be kept as small as possible. This node is one of the main sources for radiated EMI.
The feedback pin is a high impedance node and is therefore sensitive to noise. Be sure to keep all feedback
traces away from the inductor and the switch node, which are sources of noise. Also, the resistor divider should
be placed close to the FB pin. The gate pin of the external PFET should be located close to the PGATE pin.
TI also recommends using a large, continuous ground plane, particularly in higher current applications.
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