AFE5816 Datasheet, PDF (16/162 Pages) Texas Instruments – 16-Channel Ultrasound AFE

AFE5816
SBAS688D – APRIL 2015 – REVISED NOVEMBER 2015
www.ti.com
8.8 Output Interface Timing Requirements
Typical values are at T_A = 25°C, AVDD_1P8 = 1.8 V, AVDD_1P9 = 1.9 V, AVDD_3P15 = 3.15 V, DVDD_1P2 = 1.2 V,
DVDD_1P8 = 1.8 V, differential ADC clock, LVDS load C_LOAD = 5 pF, R_LOAD = 100 Ω, 14-bit ADC resolution, and sample rate
= 65 MSPS, unless otherwise noted. Minimum and maximum values are across the full temperature range of T_MIN = –40°C to
T_MAX = 85°C.
MIN
TYP
MAX UNIT
GENERAL
t_AP
δt_AP
Aperture delay⁽¹⁾
Aperture delay variation from device to device
(at same temperature and supply)
1.6
ns
±0.5
ns
t_APJ
Aperture jitter with LVPECL clock as input clock
ADC TIMING
C_d
ADC latency
Default after reset⁽¹⁾
Low-latency mode
LVDS TIMING⁽²⁾
f_F
Frame clock frequency⁽¹⁾
D_FRAME
Frame clock duty cycle
N_SER
Number of bits serialization of each ADC word
1X output data rate
mode
f_D
Output rate of serialized data
2X output data rate
mode
0.5
8.5
4.5
f_CLKIN
50%
12
N_SER × f_CLKIN
2 × N_SER × f_CLKIN
ps
ADC clocks
MHz
16
1000
1000
Bits
Mbps
f_B
Bit clock frequency
f_D / 2
500 MHz
D_BIT
t_D
t_PDI
Bit clock duty cycle
Data bit duration⁽¹⁾
Clock propagation delay⁽¹⁾
50%
1
1000 / f_D
ns
6 × t_D+ 5
ns
δt_PROP
Clock propagation delay variation from device to device
(at same temperature and supply)
±2
ns
t_ORF
DOUT, DCLK, FCLK rise and fall time, transition time
between –100 mV and +100 mV
t_OSU
Minimum serial data, serial clock setup time⁽¹⁾
t_OH
Minimum serial data, serial clock hold time⁽¹⁾
t_DV
Minimum data valid window⁽³⁾⁽¹⁾
TX_TRIG TIMING
t_{TX_TRIG_DEL}
Delay between TX_TRIG and TX_TRIGD⁽⁴⁾
t_{SU_TX_TRIGD}
Setup time related to latching TX_TRIG relative to the
rising edge of the system clock
0.2
ns
t_D / 2 – 0.4
ns
t_D / 2 – 0.4
ns
t_D – 0.65
ns
0.5
0.4 × t_S(5)
ns
0.6
ns
t_{H_TX_TRIGD}
Hold time related to latching TX_TRIG relative to the
rising edge of the system clock
0.4
ns
(1) See Figure 1.
(2) All LVDS specifications are characterized but are not tested at production.
(3) The specification for the minimum data valid window is larger than the sum of the minimum setup and hold times because there can be
a skew between the ideal transitions of the serial output data with respect to the transition of the bit clock. This skew can vary across
channels and across devices. A mechanism to correct this skew can therefore improve the setup and hold timing margins. For example,
the LVDS_DCLK_DELAY_PROG control can be used to shift the relative timing of the bit clock with respect to the data.
(4) TX_TRIGD is the internally delayed version of TX_TRIG that gets latched on the rising edge of the ADC clock.
(5) t_S is the ADC clock period in nanoseconds (ns).
16
Submit Documentation Feedback
Product Folder Links: AFE5816
Copyright © 2015, Texas Instruments Incorporated