ADS8528 Datasheet, PDF (16/51 Pages) Texas Instruments – 12-, 14-, 16-Bit, Eight-Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTERS

ADS8528
ADS8548
ADS8568
SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011
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PIN #
NAME
20
DB11/REFBUFE
N
21
DB10/SCLK
22
DB9/SDI
23
DB8/DCEN
24
DGND
25
DVDD
26
DB7
27
DB6/SEL_B
28
DB5/SEL_CD
29
DB4
30
DB3/DCIN_A
31
DB2/DCIN_B
32
DB1/DCIN_C
33
DB0/DCIN_D
34
RANGE/XCLK
35
BUSY/INT
TYPE ⁽¹⁾
DIO/DI
DIO/DI
DIO/DI
DIO/DI
P
P
DIO
DIO/DI
DIO/DI
DIO
DIO/DI
DIO/DI
DIO/DI
DIO/DI
DI/DI/DO
DO
PIN DESCRIPTIONS (continued)
DESCRIPTION
PARALLEL INTERFACE (PAR/SER = 0)
SERIAL INTERFACE (PAR/SER = 1)
Data bit 11 input/output.
Output is MSB for the ADS8528.
Hardware mode (HW/SW = 0): reference buffer
enable input.
When low, all internal reference buffers are enabled
(mandatory if internal reference is used).
When high, all reference buffers are disabled.
Software mode (HW/SW = 1): connect to
DGND or DVDD.
The internal reference buffers are controlled by bit C14
(REFBUFEN) in the Configuration Register (CONFIG).
Data bit 10 input/output
Serial interface clock input.
Data bit 9 input/output
Hardware mode (HW/SW = 0): connect to DGND.
Software mode (HW/SW = 1): serial data input.
Data bit 8 input/output
Daisy-chain enable input.
When high, DB[3:0] serve as daisy-chain inputs
DCIN_[A:D].
If daisy-chain mode is not used, connect to DGND.
Buffer I/O ground, connect to digital ground plane
Buffer I/O supply, connect to digital supply.
Decouple according to the Power Supply section.
Data bit 7 input/output
Must be connected to DGND
Data bit 6 input/output
Select SDO_B input.
When low, SDO_B is disabled and data from all eight
channels are only available through SDO_A.
When high and SEL_CD = 0, data from channel pairs B
and D are available on SDO_B. When SEL_CD = 1,
data from channel pair B are available on SDO_B.
Data bit 5 input/output
Select SDO_C and SDO_D input.
When high, data from channel pair C are available on
SDO_C while data from channel pair D are available on
SDO_D. When low and SEL_B = 1, data from channel
pairs A and C are available on SDO_A while data from
channel pairs B and D are available on SDO_B. When
low and SEL_B = 0, data from all eight channels are
avaiable on SDO_A.
Data bit 4 input/output
Connect to DGND
Data bit 3 input/output
When DCEN = 1, this pin is the daisy-chain data input
for SDO_A of the previous device in the chain. When
DCEN = 0, connect to DGND.
Data bit 2 input/output
When DCEN = 1 and SEL_B = 1, this pin is the
daisy-chain data input for SDO_B of the previous device
in the chain. When DCEN = 0, connect to DGND.
Data bit 1 input/output
When DCEN = 1 and SEL_CD = 1, this pin is the
daisy-chain data input for SDO_C of the previous
device in the chain.
When DCEN = 0, connect to DGND.
Data bit 0 (LSB) input/output
When DCEN = 1 and SEL_CD = 1, this pin is the
daisy-chain data input for SDO_D of the previous
device in the chain.
When DCEN = 0, connect to DGND.
Hardware mode (HW/SW = 0): analog input voltage range select input.
When low, the analog input voltage range is ±4VREF. When high, the analog input voltage range is ±2VREF.
Sofware mode (HW/SW = 1): this pin is an external conversion clock input if CONFIG bit C29 = 1 (CLKSEL); or an
internal conversion clock output if CONFIG bit C28 = 1 (CLKOUT_EN).
If this pin is not used, connect to DGND.
When CONFIG bit C27 = 0 (BUSY/INT) this pin is a converter busy status output.
This pin transitions high when a conversion has been started and transitions low for a single conversion clock cycle
(t_CCLK) whenever a channel pair conversion is completed and stays low when the conversion of the last channel pair
has completed.
When bit C27 = 1 (BUSY/INT in CONFIG), this pin is an interrupt output. This pin transitions high after a conversion
has been completed and remains high until the next read access. This mode can only be used if all eight channels
are sampled simultaneously (all CONVST_x tied together). The polarity of the BUSY/INT output can be changed
using bit C26 (BUSY L/H) in the Configuration Register.
16
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