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| ADS8517_14 Datasheet, PDF (16/42 Pages) Texas Instruments – 16-Bit, 200-kSPS, Low-Power, Sampling ANALOG-TO-DIGITAL CONVERTER with Internal Reference and Parallel/Serial Interface | |||
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ADS8517
SLAS527A â SEPTEMBER 2008 â REVISED JUNE 2009 ................................................................................................................................................. www.ti.com
Parallel Output (After a Conversion)
After conversion N is completed and the output registers have been updated, BUSY (pin 24) goes high. Valid
data from conversion N are available on D7-D0 (pin 9-13 and 15-17). BUSY going high can be used to latch the
data. Refer to Table 5, Figure 30, and Figure 31 for timing specifications.
t1
R/C
t3
BUSY
t6
MODE Acquire
Parallel
Previous
Data Bus High Byte Valid
Hi-Z
t9
BYTE
t4
t5
t7
Convert
t12
t11
Previous High Previous Low
Byte Valid
Byte Valid
t2
t12
Not Valid
t12
t3
t6
t8
Acquire
t10
High Byte
Valid
t12
Low Byte
Valid
t1
Convert
t12
Hi-Z
High Byte
Valid
t9
t12
Figure 30. Conversion Timing With Parallel Output (CS and DATACLK Tied Low, EXT/INT Tied High)
t21
t1
t21
R/C
CS
t3
t4
BUSY
t21
t21
t21
t21
t21
t21
BYTE
t21
t21
Data Bus
Hi-Z State
High Byte Hi-Z State Low Byte
t21
t9
t21
t9
Hi-Z State
Figure 31. CS to Control Conversion and Read Timing With Parallel Outputs
16
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