ADS8382_16 Datasheet, PDF (16/36 Pages) Texas Instruments – 18-BIT, 600-kHz, FULLY DIFFERENTIAL PSEUDO-BIPOLAR INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE AND REFERENCE

ADS8382
SLAS416B – JUNE 2004 – REVISED NOVEMBER 2004
www.ti.com
CONVST
CS
D
Q
LATCH
LATCH
CONVST_QUAL
Figure 41. Relationship Between CONVST_QUAL, CS, and CONVST
TIMING DIAGRAMS
In the following descriptions, the signal CONVST_QUAL represents CONVST latched by a low value on CS (see
Figure 41).
To avoid performance degradation, there are three quiet zones to be observed (t_quiet1 and t_quiet2 are zones before
and after the falling edge of CONVST_QUAL while t_quiet3 is a time zone before the falling edge of BUSY) where
there should be no I/O activities. Interface control signals, including the serial clock should remain steady. Typical
degradation in performance if these quiet zones are not observed is depicted in the specifications section.
To avoid data loss a read operation should not start around the BUSY falling edge. This is constrained by t_su2,
t_su3, t_h2, and t_h8.
CONVST_QUAL
t_quiet1
BUSY
t_quiet2
t_quiet3
CS
Quiet Zones
CS
t_su2
t_h2
BUSY
FS
t_su3
t_h8
BUSY
No Read Zone (FS Initiated)
No Read Zone (CS Initiated)
Figure 42. Quiet Zones and No-Read Zones
CONVERSION AND SAMPLING
1. Convert start command:
The device enters the conversion phase from the sampling phase when a falling edge is detected on
CONVST_QUAL. This is shown in Figure 43, Figure 44, and Figure 45.
2. Sample (acquisition) start command:
The device starts sampling from the wait/nap state or at the end of a conversion if CONVST is detected as
high and CS as low. This is shown in Figure 43, Figure 44, and Figure 45.
Maintaining this condition (holding CS low) when the device has just finished a conversion (as shown in
Figure 43) takes the device immediately into the sampling phase after the conversion phase (back-to-back
conversion) and hence achieves the maximum throughput. Otherwise, the device enters the wait state or the
nap state.
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