66AK2H14_16 Datasheet, PDF (16/354 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

66AK2H14/12/06
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS866E—November 2013
Table 2-1
Characteristics of the 66AK2H14/12/06 Processor (Part 2 of 2)
Process
μm
Technology
HARDWARE FEATURES
66AK2H14
66AK2H12
0.028 μm
66AK2H06
Product Status ⁽²⁾
Product Preview (PP), Advance Information (AI), Production Data
(PD)
PD
End of Table 2-1
1 The Security Accelerator function is subject to export control and will be enabled only for approved device shipments.
2 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
2.2 C66x DSP CorePac
The C66x DSP CorePac extends the performance of the C64x+ and C674x CPUs through enhancements and new
features. Many of the new features target increased performance for vector processing. The C64x+ and C674x DSPs
support 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8-bit data. On the C66x DSP, the
vector processing capability is improved by extending the width of the SIMD instructions. C66x DSPs can execute
instructions that operate on 128-bit vectors. The C66x CPU also supports SIMD for floating-point operations.
Improved vector processing capability (each instruction can process multiple data in parallel) combined with the
natural instruction level parallelism of C6000 architecture (e.g., execution of up to 8 instructions per cycle) results
in a very high level of parallelism that can be exploited by DSP programmers through the use of TI's optimized
C/C++ compiler.
For more details on the C66x CPU and its enhancements over the C64x+ and C674x architectures, see the following
documents (2.6 ‘‘Related Documentation from Texas Instruments’’ on page 19):
• C66x CPU and Instruction Set Reference Guide
• C66x DSP Cache User Guide
• C66x CorePac User Guide
2.3 ARM CorePac
The ARM CorePac of the 66AK2H14/12/06 integrates a Cortex-A15 Cluster (4 Cortex™-A15 processors) with
additional logic for bus protocol conversion, emulation, interrupt handling, and debug related enhancements. The
Cortex™-A15 processor is an ARMv7A-compatible, multi-issue out-of-order, superscalar pipeline with integrated
L1 caches. The implementation also supports advanced SIMDV2 (Neon technology) and VFPv4 (Vector Floating
Point) architecture extensions, security, virtualization, LPAE (Large Physical Address Extension), and
multiprocessing extensions. The quad core cluster includes a 4MB L2 cache and support for AMBA4 AXI and AXI
Coherence Extension (ACE) protocols. For more information see the ARM CorePac User Guide for KeyStone II
Devices User Guide listed in 2.6 ‘‘Related Documentation from Texas Instruments’’ on page 19.
2.4 Development Tools
2.4.1 Development Support
In case the customer would like to develop their own features and software on the 66AK2H14/12/06 device, TI offers
an extensive line of development tools for the TMS320C6000™ DSP platform, including tools to evaluate the
performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug
software and hardware modules. The tool's support documentation is electronically available within the Code
Composer Studio™ Integrated Development Environment (IDE).
16 Device Characteristics
Copyright 2013 Texas Instruments Incorporated
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