DM385_16 Datasheet, PDF (157/281 Pages) Texas Instruments – DaVinci Digital Media Processor

DM385, DM388
www.ti.com
SPRS821D – MARCH 2013 – REVISED DECEMBER 2013
Table 7-24. Maximum SYSCLK Clock Frequencies (continued)
SYSCLK
SYSCLK18
SYSCLK19
SYSCLK20
SYSCLK21
SYSCLK22
SYSCLK23
MAX CLOCK FREQUENCY
OPP100 (MHz)
0.032768
192
192
192
RSV
RSV
7.4.8 Module Clocks
Device Modules either receive their clock directly from an external clock input, directly from a PLL, or from
a PRCM SYSCLK output. Table 7-25 lists the clock source options for each Module on this device, along
with the maximum frequency that Module can accept. To ensure proper Module functionality, the device
PLLs and dividers must be programmed not to exceed the maximum frequencies listed in this table.
Table 7-25. Maximum Module Clock Frequencies
MODULE
Cortex-A8
DDR0
DMM
EDMA
EMAC Switch (GMII)
EMAC Switch (RGMII)
EMAC Switch (RMII and MII)
Face Detect
GPIO
GPIO Debounce
GPMC
HDMI
HDMI CEC
HDMI I2S
HDVICP2
HDVPSS
HDVPSS VOUT1
HDVPSS VOUT0
HDVPSS SD VENC
HDVPSS HD VENC
I2C0/1/2/3
ISS
L3 Fast
CLOCK SOURCE(S)
PLL_ARM
SYSCLK18
PLL_DDR
PLL_DDR/2
SYSCLK4
SERDES
PLL_VIDEO0
PLL_VIDEO0
SERDES
SERDES
PLL_VIDEO0
EMAC_RMREFCLK Pin
SYSCLK4
SYSCLK6
SYSCLK18
SYSCLK6
PLL_VIDEO2
SYSCLK10
SYSCLK20
SYSCLK21
AUD_CLK0/1/2
AUX Clock
SYSCLK3
PLL_HDVPSS
PLL_VIDEO2
HDMI PHY
PLL_VIDEO1
PLL_VIDEO2
PLL_VIDEO0
PLL_VIDEO0
PLL_VIDEO1
HDMI
SYSCLK10
PLL_ MEDIACTL
SYSCLK4
MAX FREQUENCY
OPP100 (MHz)
600
400
200
220
Fixed 125
Fixed 250
Fixed 50
220
110
Fixed 0.032768
110
186
Fixed 48
50
266
200
186
165
Fixed 54
Fixed 148.5
48
400
220
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Power, Reset, Clocking, and Interrupts 157
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